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As the progress of the packaging technology for the electronic consuming devices, the customer demands more and more. From the trend of the development on electronic devices, it shows that these demands require for more functions or higher density of devices within a limited space. By the capabilities of the 3D-IC technology, it could support such a design with multi-purposes including a smaller size, the high-speed and multi-functions. There are many approaches and technologies to make the 3D-IC. Amount of them, the stacking with Through-Silicon-Via (TSV), plays a very important role. It shortens the path of the circuit in a device. And hence, this device may support a faster operation. In this study, we analyze the different designs based on two TSV technologies, the Cu-filled and coaxial-type TSVs. By using the simulation approach, we evaluate the performances of these proposed designs. And, the results in our study should have the benefits for designing the interposer substrates which are used for developing the 3D-IC.

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The memory storage technology revolution has taken the consumer electronics by a storm in just two years. The volatile memory Dynamic Random Access Memory (DRAM) for PC and notebook computing and gaming are increasing in density and speed. With all these improvement, the memory device packaging technology is also evolving rapidly, from the leadframe packages to BGA packages [2]. Under high frequency operation, the parasitics associated with package will significantly degrade the package performance. The DRAM packages are used primarily in the fabrication of DIMM modules that are inserted to the motherboards in PC and notebook computers. With newer DRAM technology in double date rate (DDR) and its second generation, DDR2, to be deployed just two years, it has higher clock rate and I/O number. Packages therefore are changing form the leadframe TSOP type 2 to faster CSPs such as fine pitch BGA (FBGA) and chip on substrate BGA (COSBGA). This paper is focused the COSBGA package [3,4]. In this paper, the packages electrical model have been established and performs signal integrity (SI) simulation. The COSBGA has smallest parasitics when comparison with other two packages. This paper also compares the performance of the COSBGA, TFBGA and TSOPII from crosstalk noise, time skew, insertion loss and return loss for IC designer reference.

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