Efficient testing and diagnosis of faulty power switches in SOCs

Abstract

DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal. If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the "Taverne" license above, please follow below link for the End User Agreement:

BIST design of power switch

“…In addition, compared with the previous designs [2,4], the test patterns are much simpler and the test results are much easier to be identified. If the signal Out is high, the tested switches and DT are fault-free, or else some of them are faulty.…”

“…But if stuck-open fault occurs in too many switches, the driving of the switches in the power domain will not be enough, and the IR drop problem is introduced which will decrease the SoC performance. The first DFT solution is reported in [2] which can test switches in both fine-grain and coarse-grain designs. But the first DFT solution suffers from the problem of long discharge time [3].…”

Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

“…The preferred method is to insert DFT control and observation points at the power switches in order to deterministically detect failures through comparison of the voltage at each power switch output with a reference voltage. One example of DFT implementations can be found in [25]. However, this technique suffers from long discharge time that may either lead to false pass or long test time.…”

Low power testing - What can commercial DFT tools provide?

“…The preferred method is to insert DFT observation points at the power switch outputs in order to deterministically detect failures through comparison of the voltage at each power switch output with a reference voltage. One of such implementations can be found in [9].…”