Efficient single-chip implementation of SHA-384 and SHA-512

McLoone, M.; McCanny, J.V.

doi:10.1109/fpt.2002.1188699

Cited by 44 publications

(35 citation statements)

References 2 publications

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“…Additionally, due to some pre-computation techniques, we are able to achieve clock frequencies higher than [10] and slightly less than [9] while at the same time significantly reducing the hardware costs.…”

Section: Comparison With Published Implementationsmentioning

confidence: 85%

“…We now compare our architectures with previously published stand-alone and multi-mode SHA-2 implementations [9,10] (see Table 2). …”

Section: Comparison With Published Implementationsmentioning

confidence: 97%

“…In all of these designs, 16-32 clock cycles are required for the padder to process an input message block before computation begins. This is avoided in our system thanks to an 'on-the-fly' padder that allows a clock cycle reduction of up to 25% compared to [10].…”

Section: Comparison With Published Implementationsmentioning

confidence: 99%

“…Ref. [10] discusses a pipelined approach to a single chip SHA-384/512 architecture. Another implementation of the SHA-512 function can be found in [11].…”

Section: Comparison With Published Implementationsmentioning

confidence: 99%

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Multi-mode operator for SHA-2 hash functions

Glabb

Imbert

Jullien

et al. 2007

Journal of Systems Architecture

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We propose an improved implementation of the SHA-2 hash family, with minimal operator latency and reduced hardware requirements. We also propose a high frequency version at the cost of only two cycles of latency per message. Finally we present a multi-mode architecture able to perform either a SHA-384 or SHA-512 hash or to behave as two independent SHA-224 or SHA-256 operators. Such capability adds increased flexibility for applications ranging from a server running multiple streams to independent pseudorandom number generation. We also demonstrate that our architecture achieves a performance comparable to separate implementations while requiring much less hardware.

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Section: Comparison With Published Implementationsmentioning

confidence: 85%

“…We now compare our architectures with previously published stand-alone and multi-mode SHA-2 implementations [9,10] (see Table 2). …”

Section: Comparison With Published Implementationsmentioning

confidence: 97%

Section: Comparison With Published Implementationsmentioning

confidence: 99%

“…Ref. [10] discusses a pipelined approach to a single chip SHA-384/512 architecture. Another implementation of the SHA-512 function can be found in [11].…”

Section: Comparison With Published Implementationsmentioning

confidence: 99%

See 2 more Smart Citations

Multi-mode operator for SHA-2 hash functions

Glabb

Imbert

Jullien

et al. 2007

Journal of Systems Architecture

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“…In [21] a single chip implementation of SHA-384 and SHA-512 based on FPGAs is introduced. A SHA-256 processor is presented in [22], also employing FPGAs for its implementation.…”

Section: Related Workmentioning

confidence: 99%

Efficient fault tolerant SHA-2 hash functions for space applications

Juliato

Gebotys

Elbaz

2009

2009 IEEE Aerospace Conference

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Abstract-Satellites are extensively used by public and private sectors to support a variety of services. Considering the cost and the strategic importance of these spacecrafts, it is fundamental to utilize strong cryptographic primitives to assure their security. However, it is of utmost importance to consider fault tolerance in their designs due to the harsh environment found in space, while keeping low area and power consumption. Therefore, this paper proposes novel fault tolerant schemes for the SHA-2 family of hash functions and analyzes their resistance to SEUs. Results obtained through FPGA implementation show that our best fault tolerant scheme for SHA-512 uses up to 32% less area and consumes up to 43% less power than the commonly used TMR technique. Moreover, its memory and registers are 435 and 175 times more resistant to SEUs than TMR. These results are crucial for supporting low area and low power fault tolerant cryptographic primitives in satellites.

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Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview

Acosta

Addabbo

Tena-Sánchez

2016

Circuit Theory & Apps

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We provide an overview of selected crypto-hardware devices, with a special reference to the lightweight electronic implementation of encryption/decryption schemes, hash functions, and true random number generators. In detail, we discuss the hardware implementation of the chief algorithms used in private-key cryptography, public-key cryptography, and hash functions, discussing some important security issues in electronic crypto-devices, related to side-channel attacks (SCAs), fault injection attacks, and the corresponding design countermeasures that can be taken. Finally, we present an overview about the hardware implementation of true random number generators, discussing the chief electronic sources of randomness and the types of post-processing techniques used to improve the statistical characteristics of the generated random sequences.A. J. ACOSTA, T. ADDABBO AND E. TENA-SÁNCHEZ resource consumption. This matter sets the point for the lightweight cryptography, that is, the subfield of cryptography aiming to provide solutions tailored for resource-constrained devices.According to Elsevier Scopus, the largest database of research peer-reviewed literature, since 2010, about 40k documents are returned if searching the keyword 'cryptography' [6]. A huge subset of these papers deals with conceptual, algorithmic, software, hardware solutions that may be taken into account in lightweight cryptography. In the face of such a vast literature, in this work, we provide a brief overview of selected crypto-hardware devices, with a special reference to the lightweight electronic implementation of encryption/decryption schemes, hash functions, and true random number generators (TRNGs).This paper is organized as in the following. In Section 2, we introduce some terminology and present an overview of the hardware implementation of the chief algorithms used in private-key cryptography, public-key cryptography (PKC), and hash functions. In Sections 3 and 4, we introduce some important security concerns about electronic crypto-devices, discussing SCAs, fault injection attacks, and the corresponding countermeasures that can be taken in the hardware design. Finally, Sections 5-8 are devised to provide an overview about the electronic implementation of TRNGs. In detail, in Sections 5 and 6, we discuss about security flaws, statistical defects, and predictability of TRNGs, presenting the chief sources of randomness used nowadays for their hardware implementation. In Sections 7 and 8, we discuss an overview of the different post-processing techniques aimed to improve the statistical characteristics of the generated random sequences and the evaluation methods used to assess the reliability of cryptographic TRNGs. Conclusion and References close the paper. CRYPTOGRAPHIC ALGORITHMSCryptographic algorithms aim to convert secret data into an unreadable code for non authorized persons, protecting secret information from theft or alteration and also enabling authentication. For better understanding, in the next sections, we define the following...

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Efficient single-chip implementation of SHA-384 and SHA-512

Cited by 44 publications

References 2 publications

Multi-mode operator for SHA-2 hash functions

Multi-mode operator for SHA-2 hash functions

Efficient fault tolerant SHA-2 hash functions for space applications

Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview

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