Multi-mode operator for SHA-2 hash functions

Abstract

We propose an improved implementation of the SHA-2 hash family, with minimal operator latency and reduced hardware requirements. We also propose a high frequency version at the cost of only two cycles of latency per message. Finally we present a multi-mode architecture able to perform either a SHA-384 or SHA-512 hash or to behave as two independent SHA-224 or SHA-256 operators. Such capability adds increased flexibility for applications ranging from a server running multiple streams to independent pseudorandom number generation. We also demonstrate that our architecture achieves a performance comparable to separate implementations while requiring much less hardware.

Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms

“…In order to take advantage of the use of specialized cores or embedded systems, several architectures have been reported to iteratively operate without using parallelization or unrolling of the inner loop [8]. Other approaches consist on introducing a pre-computing stage in order to reduce the critical path.…”

“…The proposed architectures can be seen as single unrolled designs thus can be used as basis to explore architectures with several unrolled rounds. There are several commercial and academic implementations of the SHA-256 algorithm reported in the literature [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. For the commercial implementations reported in [11] and [12], internal details of the architectures are not reported, thus they will not be included in the discussion.…”

“…Academic implementations are based on several approaches such as straightforward design, unrolled/pipelined designs, hardware/software implementations and designs using pre-computations. Because this work proposes some modifications to the way the operations of the inner loop are performed, only architectures that were implemented using similar approaches are briefly described [8,10,16,17,18]. Some features of these works are listed in Table 3.…”

Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate

“…Glabb [8] describes an architecture that utilizes the similarity in processing of SHA-2s in implementation. The 64-bit data processing of SHA-384/512 is divided into two 32-bit data processing of SHA-224/256.…”

“…However, the un- rolling architecture will increase the hardware size and decrease the frequency due to extra computations in each step. Multi-mode is given by Glabb [8] and Helion [13] but their performance rates are not really good due to complexity and low frequency. This paper describes fine-grained pipelining multimode SHA-384/512 architecture on FPGA in which one iteration computations of E and A (see Fig.…”