Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms

Algredo‐Badillo, Ignacio; Feregrino-Uribe, Claudia; Cumplido, René; Morales-Sandoval, Miguel

doi:10.1109/dsd.2011.75

Cited by 4 publications

(7 citation statements)

References 10 publications

(22 reference statements)

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“…This architecture is further optimised in [72] by observing that, due to data dependencies, the whole round function can be computed using only two CSAs without incurring any performance penalty, by properly scheduling the various additions. In [86], a reordering within the transformation round is proposed. The following variable is defined…”

Section: A Basic Architecturesmentioning

confidence: 99%

“…The work in [86] pushes this approach further, proposing another precomputation based on the fact that D t = C t−1 again due to Equation (IV.1). The quantity τ t defined in Equation (V.1) can be precomputed during round t − 1 as 5…”

Section: Architectures With Precomputationmentioning

confidence: 99%

“…In [86] three architectures are compared against the straightforward implementation of Equations (II.6) to (II.11) with a common platform, which employs a rolling loop to perform the whole SHA-256 computation. The three architectures considered in [86] include the scheme resulting from Equations (V.1) and (V.2) originally proposed in [84], the one resulting from Equations (V.3) and (V.4), and the one resulting from Equations (V.5) and (V.6).…”

Section: Architectures With Precomputationmentioning

confidence: 99%

“…To stress the fact that Equation (V.5) is computed at round t − 1 while Equation (V.1) is computed at round t,[86] calls the latter δ t instead of τ t…”

mentioning

confidence: 99%

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SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey

Martino

Cilardo

2020

IEEE Access

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While SHA-2 is a ubiquitous cryptographic hashing primitive, its role in emerging application domains, e.g. blockchains or trusted IoT components, has made the acceleration of SHA-2 very challenging due to new stringent classes of requirements, especially implementation cost and energy efficiency. The survey discusses these emerging applications and their fundamental requirements. Then, the work presents a comprehensive review of the different design techniques available in the literature for SHA-2 acceleration. The main focus of the presentation is placed on the impact of each design technique on the area, energy, power, and performance of the resulting accelerator, guiding the designer through the identification of the appropriate technique mixes which meet the constraints of any given application.

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Section: A Basic Architecturesmentioning

confidence: 99%

Section: Architectures With Precomputationmentioning

confidence: 99%

Section: Architectures With Precomputationmentioning

confidence: 99%

“…To stress the fact that Equation (V.5) is computed at round t − 1 while Equation (V.1) is computed at round t,[86] calls the latter δ t instead of τ t…”

mentioning

confidence: 99%

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SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey

Martino

Cilardo

2020

IEEE Access

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“…As below, we separately discuss other implementations of SHA-256 circuit and other implementations of HMAC-SHA-256 circuit. 6.1.1 Scan-based Attack against Other SHA-256 Circuit Implementations As far as we know, basic iterative SHA-256 circuit [29], [40], two-unrolled SHA-256 circuit [41], [42], pipelining SHA-256 circuit [43], [44], two-unrolled pipelining SHA-256 circuit [45], four-unrolled pipelining SHA-256 circuit [45], and compact SHA-256 circuit [46] are proposed as SHA-256 circuit implementations.…”

Section: Scan-based Attack Against Other Sha-256/hmac-sha-256 Circuitmentioning

confidence: 99%

Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures

Oku

Yanagisawa

Togawa

2018

IPSJ Transactions on System LSI Design Methodology

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Abstract:A scan chain is used by scan-path test, one of design-for-test techniques, which can control and observe internal registers in an LSI chip. On the other hand, a scan-based side-channel attack is focused on which can restore secret information by exploiting the scan data obtained from a scan chain inside the crypto chip during cryptographic processing. In this paper, we propose a scan-based attack method against a hash generator circuit called HMAC-SHA-256. Our proposed method is composed of three steps; Firstly, we isolate 64 bit-transition groups from a scan data using scan signatures based on the property of the HMAC-SHA-256 algorithm. Secondly, we classify these 64 bittransition groups into 32 pairs. Lastly, we find out the correspondence between the scan data and the internal registers in the target HMAC-SHA-256 circuit. Our proposed method restores the secret information by the three steps above, even if the scan chain includes registers other than the target hash generator circuit and hence it becomes too long. Experimental results show that our proposed method successfully restores two secret keys of the HMAC-SHA-256 circuit using up to 425 input messages in 7.5 hours.

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A High-Performance Multimem SHA-256 Accelerator for Society 5.0

2021

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The development of a low-cost high-performance secure hash algorithm (SHA)-256 accelerator has recently received extensive interest because SHA-256 is important in widespread applications, such as cryptocurrencies, data security, data integrity, and digital signatures. Unfortunately, most current researches have focused on the performance of the SHA-256 accelerator but not on a system level, in which the data transfer between the external memory and accelerator occupies a large time fraction. In this paper, we solve the state-of-art problem with a novel SHA-256 architecture named the multimem SHA-256 accelerator that achieves high performance at the system on chip (SoC) level. Notably, our accelerator employs three novel techniques, the pipelined arithmetic logic unit (ALU), multimem processing element (PE), and shift buffer in shift buffer out (SBi-SBo), to reduce the critical path delay and significantly increase the processing rate. Experiments on a field-programmable gate array (FPGA) and an applicationspecific integrated circuit (ASIC) show that the proposed accelerator achieves significantly better processing rate and hardware efficiency than previous works. The accelerator accuracy is verified on a real hardware platform (FPGA ZCU102). The accelerator is synthesized and laid out with 180 nm complementary metal oxide semiconductor (CMOS) technology with a chip sized 8.5mm × 8.5mm, consumes 1.86 W, and provides a maximum processing rate of 40.96 Gbps at 80 MHz and 1.8 V. With FPGA Xilinx 16 nm FinFET technology, the accelerator processing rate is as high as 284 Gbps.

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Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms

Cited by 4 publications

References 10 publications

SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey

SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey

Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures

A High-Performance Multimem SHA-256 Accelerator for Society 5.0

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