Efficient selection and analysis of critical-reliability paths and gates

A cross-layer SER analysis in the presence of PVTA variations

“…The authors of [19] proposed a novel instance-based BTI analysis technique. Library-based and LUT-based aging techniques are presented in [69,68,19,70,30]. The impact of workload on aging, and runtime variations are analyzed in [71,19] and [68], respectively.…”

“…For PVTA analysis, we mainly use the models/methods presented in [70,24,66,67,19,75,69,32,30,68,66,80,81,71]. According to Fig.…”

“…Voltage variation (voltage drop) is mainly a consequence of changes in the workload-dependent supply current drawn from nonzero resistance and inductance of supply wires that lead to IR-drop and di=dt, respectively. Transistor aging (e.g., NBTI, PBTI, and HCI) increases the absolute value of the threshold voltage of transistors which leads to degradation of transistors driving current over time [27][28][29][30]. Note that transistor aging depends on PVT variations, logic probability (LP) and Toggling Rate (TR) of transistors which are determined based on workload [31,27,32,33].…”

Cross-layer custom instruction selection to address PVTA variations and soft error

“…In library-based STA approach, we integrate the techniques presented in [51,29,56]. However, we extended the previous techniques such that our library is compatible with standard CCS timing library model and also we capture the combined impacts of all sources of PVTA variations.…”

Representative critical reliability paths for low-cost and accurate on-chip aging evaluation

“…As aging-aware Spice simulation is extremely time con- suming, we developed an in-house tool for aging-aware path delay analysis at design time [18]. This tool generates a lookup- Complexity of the synthesis flow mainly comes from the singular value decomposition for matrix P .…”