Representative critical reliability paths for low-cost and accurate on-chip aging evaluation

Abstract

Aging of transistors degrades circuit performance and can potentially lead to functional failure in the field. This has become a major reliability concern especially when technology further scales to 45 nm and below. It is thus necessary to design on-chip structures that can provide accurate aging evaluation with no performance penalty. In this paper, we propose a novel methodology to accurately evaluate aging in the field. Representative Critical Reliability Paths (RCRPs) are synthesized as a stand-alone circuit to represent the aging of critical reliability paths, which are defined as paths that can potentially become critical at some point in time due to aging. By monitoring the RCRPs, aging of the critical reliability paths can be efficiently and accurately evaluated with no impact on the normal operation of the chip. The aging evaluation results can then be exploited to guide on-chip performance calibration to ensure lifetime reliability. Simulation results demonstrate the efficiency of the proposed structure.

Predicting circuit aging using ring oscillators

“…Existing work on RCPs for aging uses different methodologies, libraries and delay models. However, as pointed out earlier, the best proposed approach [7] requires significantly more computation than our method and entails complex layout issues. Moreover, our work is easier to implement in an industrial setting where ROSC-based methodologies have been in use for years.…”

“…The final column lists the total CPU time, τ , that is required to compute the value of D for each CUT, evaluated on a 64-bit Ubuntu server (Intel ® Core™2 Duo CPU E8400 3GHz). The modest runtimes (significantly faster than RCP procedures in, e.g., [7]) indicate the aptness of our method for handling very large CUTs. Thus, during design time, these D values can be computed cheaply and stored in look-up tables for each CUT, using which one can estimate its delay degradation at any point of time based on a cheap measurement of ROSC delay degradation.…”

“…First, ROSCs are compact and uniform, and require the design and layout of only a single repeatable macrocell, as against RCPs, which must be designed and laid out individually. Second, the process of generating RCP circuits is computationally expensive (for circuit b15, RCP generation can take 30 minutes [7], as against this work, where the computational effort for ROSC characterization takes less than two seconds).…”

“…These range from simple ring oscillators (ROSCs) [4], [5] to more complex representative critical path (RCP) circuits [6], [7], [8].…”

ReSCALE: Recalibrating sensor circuits for aging and lifetime estimation under BTI

“…As a result, chip design teams often treat SP-based methods with skepticism. Post-silicon techniques, on the other hand, rely on data from surrogate aging sensors [2]- [4], such as ring oscillators, to apply just enough adaptive compensation to mitigate the effect of aging [5], [6]. To a limited extent, they may successfully capture the environment faced by the circuit, e.g., if they are placed close to the circuit and have a similar connection to the power grid, they can capture the thermal and supply voltage environment.…”