Efficient partial enumeration for timing analysis of asynchronous systems

Abstract

- I IntroductionEfficient timing verification algorithms are essential in the development of correctly working concurrent systems. Our work is mainly motivated by the need to verify asynchronous circuits where correctness of a design may depend on both functional and timing aspects. For example, some design methods, such as those for timed circuits [9], directly use timing information for optimization. Other design methods rely on delay information for the removal of hazards [8] or to ensure a fundamental mode of operation [14]. Timing verification can be a computationally expensive task due to exponential factors introduced by state enumeration and timing considerations.The verification problems that we consider require timed reachability analysis. An approach to this is geometric timing analysis (GTA). GTA algorithms have been studied by Berthomieu [2], Dill [5], Alur [1], among others. These methods can be relatively efficient in practice, but for highly concurrent systems, they can still be prohibitively expensive due to state explosion exponential in the concurrency parameter.The GTA approach of Rokicki [10] improves on the basic procedure, but it suffers still from significant complexity problems, since it also traverses the complete state space. Related work by Hulgaard and Burns [7] is very efficient, but does not address verification problems that require reachability analysis and thus can not be directly compared with GTA methods.To address the complexity problems in GTA, we propose an efficient state space traversal algorithm for the timing analysis of concurrent systems, modeled using a labeled timed Petri net (TPN). The TPN model used may combine different combinations of choice and concurrency, within a class of n-safe nets.Our method offers a key improvement compared to existing GTA work by taking into account and exploitingindependence information such that it suffices to traverse the state space only partially. It relies on the pre-mature firing concept, using a modified geometric representation, which incorporates an extended notion of clocks with a negative age. The canonization of the geometric regions required during each step of the enumeration is also extended to account for these two concepts. Since our GTA algorithm relies on partial enumeration of the state space, it requires path selection. Hence, we have developed several path selection heuristics.Due to space limitation this paper focuses only on the analysis aspects. However we would like to stress that our formalism also includes notions of specification, circuit composition, and refinement pre-orders, required for timed circuit verification.Experiments using our fully automated method show that for problems involving a high degree of concurrency, our approach indeed offers significant improvement over existing methods. Petri nets with more than 6000 nodes and 10 210 reachable states have been analyzed using the proposed method.Section II gives the formal terminology. Section III examines GTA and its complexity problems i...

Timed circuit verification using TEL structures

“…In highly concurrent systems, where many interleavings are possible, the number of geometric regions per untimed state can be huge. Some researchers [8]- [10], [27] have attacked this problem by reducing the number of interleavings explored using the partial order techniques developed for untimed systems. These algorithms compute a set of event firings that must be interleaved to ensure that the desired property is checked.…”

“…If most interleavings need to be explored, these techniques could still result in state explosion. The algorithms from [10] and [27] do address the problem of generating a unique region for every firing sequence. However, since these techniques do not find the entire state space, they cannot be applied to synthesis.…”

Difference Decision Diagrams

“…Although DBMs provide a compact representation of a clock configuration, there are several serious problems with the approaches based on DBMs: (1) the number of DBMs for representing the timing information associated with a given state can become very large, (2) there is no sharing or reuse of DBMs among the different discrete states, and (3) each discrete state is represented explicitly, thus these approaches are limited by the number of reachable states of the system. Several researchers have attempted to remedy these shortcomings, for example by using partial order methods [5,18,20] or by using approximate methods [3,4,21]. Although these approaches do address problem (1), they are still susceptible to problems (2) and (3) since each state is represented explicitly.…”

Formal verification of safety properties in timed circuits

“…The calculation of the language generated by a timed system is proven to be PSPACE-complete [1], and demonstrated to be highly complex in several contexts such as real-time systems [1,15] and asynchronous circuits [13,9,16,18,24,27]. Difference bounds matrices [5] and decision diagrams [8] have been used to efficiently represent timed polyhedra.…”