The SFG-Tracing methodology [5] addresses the automatic verification of digital synchronous circuit implementations as specified at the algorithmic level as signal-(SFG) or data flow graphs. The SFG-Tracing methodology is a multi-level design verification paradigm that aims at bridging the gap between higher level specifications down to lower level implementations up to the transistor switch level. In this paper the concepts of the SFG-Tracing methodology are illustrated by the automatic verification of a transistor level implementation of a small chip generated from its high level specification by the CATHEDRAL-I1 silicon compiler. This application, although simple, includes a datapath, register files, a multi-branch micro coded controller, and additional circuitry as necessary for Design for Testability measures. This application illustrates the SFG-Tracing verification methodology as applied to one member of a partitioned SFG behavioral specification. Experimental results on more complex, completely verified designs of 32000 transistors demonstrate the feasibility of the approach.
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I IntroductionEfficient timing verification algorithms are essential in the development of correctly working concurrent systems. Our work is mainly motivated by the need to verify asynchronous circuits where correctness of a design may depend on both functional and timing aspects. For example, some design methods, such as those for timed circuits [9], directly use timing information for optimization. Other design methods rely on delay information for the removal of hazards [8] or to ensure a fundamental mode of operation [14]. Timing verification can be a computationally expensive task due to exponential factors introduced by state enumeration and timing considerations.The verification problems that we consider require timed reachability analysis. An approach to this is geometric timing analysis (GTA). GTA algorithms have been studied by Berthomieu [2], Dill [5], Alur [1], among others. These methods can be relatively efficient in practice, but for highly concurrent systems, they can still be prohibitively expensive due to state explosion exponential in the concurrency parameter.The GTA approach of Rokicki [10] improves on the basic procedure, but it suffers still from significant complexity problems, since it also traverses the complete state space. Related work by Hulgaard and Burns [7] is very efficient, but does not address verification problems that require reachability analysis and thus can not be directly compared with GTA methods.To address the complexity problems in GTA, we propose an efficient state space traversal algorithm for the timing analysis of concurrent systems, modeled using a labeled timed Petri net (TPN). The TPN model used may combine different combinations of choice and concurrency, within a class of n-safe nets.Our method offers a key improvement compared to existing GTA work by taking into account and exploitingindependence information such that it suffices to traverse the state space only partially. It relies on the pre-mature firing concept, using a modified geometric representation, which incorporates an extended notion of clocks with a negative age. The canonization of the geometric regions required during each step of the enumeration is also extended to account for these two concepts. Since our GTA algorithm relies on partial enumeration of the state space, it requires path selection. Hence, we have developed several path selection heuristics.Due to space limitation this paper focuses only on the analysis aspects. However we would like to stress that our formalism also includes notions of specification, circuit composition, and refinement pre-orders, required for timed circuit verification.Experiments using our fully automated method show that for problems involving a high degree of concurrency, our approach indeed offers significant improvement over existing methods. Petri nets with more than 6000 nodes and 10 210 reachable states have been analyzed using the proposed method.Section II gives the formal terminology. Section III examines GTA and its complexity problems i...
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