Efficient Mitigation of Data and Control Flow Errors in Microprocessors

Abstract

Abstract-The use of microprocessor-based systems is gaining importance in application domains where safety is a must. For this reason, there is a growing concern about the mitigation of SEU and SET effects. This paper presents a new hybrid technique aimed to protect both the data and the control-flow of embedded applications running on microprocessors. On one hand, the approach is based on software redundancy techniques for correcting errors produced in the data. On the other hand, control-flow errors can be detected by reusing the on-chip debug interface, existing in most modern microprocessors. Experimental results show an important increase in the system reliability even superior to two orders of magnitude, in terms of mitigation of both SEUs and SETs. Furthermore, the overheads incurred by our technique can be perfectly assumable in low-cost systems.

A New Hybrid Nonintrusive Error-Detection Technique Using Dual Control-Flow Monitoring

“…In such scenario, the goal is to achieve good error coverage with the smallest additional hardware and a reduced performance decrease. Many different approaches can be found in the literature [4]- [9].…”

“…Hybrid techniques [4]- [9] combine hardware and software fault-tolerance techniques in order to improve error detection and reduce the performance degradation that software techniques entail. Hybrid fault tolerance techniques typically consist in adding an external module, often known as a watchdog processor, to monitor the execution of instructions in the processor.…”

“…Hybrid fault tolerance techniques typically consist in adding an external module, often known as a watchdog processor, to monitor the execution of instructions in the processor. To this purpose, the hardware monitor is connected to the bus between the memory and the microprocessor [4], [5], [8] or to the trace interface [7], [9], [10]. In the first case, the control flow is monitored at the first pipeline stage (instruction fetch), while in the second case the control flow is monitored at the last pipeline stage after the instruction has been executed.…”

Soft‐error reliable architecture for future microprocessors

“…In [28], Meixner and Sorin have done CFC in software and redundancy on hardware by duplicating the hardware modules. In [29], Parra et al have done the reverse. An additional hardware module is used to check the CFC and redundancy is done at the software level.…”

Fault tolerant electronic system design

“…In the experiments, the same approach as in [42] and [53] was adopted to evaluate the error detection capabilities. We estimate the global error rate using fault injection.…”