Efficient Hardware Design of Iterative Stencil Loops

Abstract

obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.uk Abstract-A large number of algorithms for multidimensional signals processing and scientific computation come in the form of iterative stencil loops (ISLs), whose data dependencies span across multiple iterations. Because of their complex inner structure, automatic hardware acceleration of such algorithms is traditionally considered as a difficult task.In this paper, we introduce an automatic design flow that identifies, in a wide family of bidimensional data processing algorithms, sub-portions that exhibit a kind of parallelism close to that of ISLs; these are mapped onto a space of highly optimized ad-hoc architectures, which is efficiently explored to identify the best implementations with respect to both area and throughput. Experimental results show that the proposed methodology generates circuits whose performance is comparable to that of manually-optimized solutions, and orders of magnitude higher than those generated by commercial HLS tools.

Dcmi

“…In this section, we provide an example that illustrates why the DCMI acceleration strategy is superior to current state-of-the-art FPGA-based accelerators [4,40]. We first explain the operation of the stencil compute kernel in Section 2.1.…”

“…The two main sources of parallelism in ISLs are spatial and temporal parallelism. Broadly, two main approaches have been proposed for exploiting both forms of parallelism in FPGA-based accelerators, and Streaming Time-Steps (SST) [4] and the Cone-based Architecture (CA) [40] are representative of these two strategies. In this section, we show that both SST and CA are inefficient, because they perform redundant computation and use OCM inefficiently.…”

“…In this section, we show that both SST and CA are inefficient, because they perform redundant computation and use OCM inefficiently. We refer to the number of time-steps that an acceleration scheme harvests parallelism from as the iteration depth D. Figure 2 shows how SST [4] and CA [40] would accelerate a 1D three-point stencil. SST exploits temporal parallelism by instantiating an accelerator core for each time-step and connecting the output of one core to the input of the next core.…”

“…First, the accelerator can exploit that inner-loop computations can be performed in parallel as long as an output element is not used as an input element within the same time-step. Intra-time-step dependencies-or spatial dependencies-can commonly be avoided by using a double-buffering strategy [40]. Second, the accelerator can exploit that the same computation is carried out in successive time-steps (i.e., several iterations of the outer loop).…”

“…The second architectural approach is exemplified by the Cone-based Architecture (CA) [40]. CA exploits that the input elements of a single output element forms a cone that expands through prior iterations.…”