Efficient FFT engine with reduced addressing logic

Xiao, Xin; Oruklu, Erdal; Saniie, Jafar

doi:10.1109/eit.2007.4374500

Cited by 5 publications

(6 citation statements)

References 13 publications

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“…Table III shows the dynamic switching power results obtained by Synopsys Power Compiler for FFT transform sizes ranging from 16 to 512. The proposed FFT architecture is compared to the existing FFT architecture given in [7]. It can be seen that, switching activity reduces significantly (more than 70% for >512-point FFT operations).…”

Section: Resultsmentioning

confidence: 92%

“…PROPOSED NEW ADDRESSING SCHEME In [7], a hardware-efficient FFT engine with reduced addressing logic was introduced by using a butterfly structure that modifies the conventional one by adding exchange control circuits at the input and output of the butterfly. With this architecture, the two inputs and two outputs of any butterfly can be exchanged; hence, all data and addresses in FFT processing can be reordered.…”

Section: Radix-2 Fft and Address Generation Logicmentioning

confidence: 99%

“…Several addressing algorithms [5][6][7]13] have been proposed to realize the conflict free data accessing. The contribution of this paper is to design a new FFT processor which reduces the power consumption by using multi-bank memories and reducing twiddle factor accessing times.…”

Section: Radix-2 Fft and Address Generation Logicmentioning

confidence: 99%

“…Based on Cohen's method, Ma's [6] algorithm can speedup the radix-2 FFT operation by reducing the address generation delay. Xiao et al [7] developed a new butterfly structure which leads to an even faster and simpler control logic for radix-2 FFT.…”

Section: Introductionmentioning

confidence: 99%

“…Gate-level algorithms [11,12] have been also proposed to reduce the FFT processor's power consumption by lower supply voltage techniques and/or voltage scaling. This paper presents a new FFT data and coefficient addressing method based on algorithm given in [7] in order to reduce switching activity and dynamic power consumption. In general, dynamic power consumption in CMOS circuits can be characterized by the following equation:…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Low-power memory addressing scheme for fast fourier transform processors

Xiao

Oruklu

Saniie

2009

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

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In this paper, a new memory addressing architecture is proposed for low-power radix-2 FFT implementations. Two optimization schemes are presented for dynamic power reduction. First, a multi-bank memory structure is introduced. Second, twiddle factor access times are significantly reduced with a new addressing sequence. For performance evaluation, FFT kernels with transform sizes ranging from 16 to 512 are implemented in CMOS 0.18µ technology. The synthesis results and architectural analysis indicate significant switching power reduction with no performance penalty. Power reduction factor grows with the transform size, making this architecture ideal for applications requiring long FFT operations.

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Section: Resultsmentioning

confidence: 92%

Section: Radix-2 Fft and Address Generation Logicmentioning

confidence: 99%