This paper presents a pipelined, reduced memory and low power CORDIC-based architecture for fast Fourier transform implementation. The proposed algorithm utilizes a new addressing scheme and the associated angle generator logic in order to remove any ROM usage for storing twiddle factors. As a case study, the radix-2 and radix-4 FFT algorithms have been implemented on FPGA hardware. The synthesis results match the theoretical analysis and it can be observed that more than 20% reduction can be achieved in total memory logic. In addition, the dynamic power consumption can be reduced by as much as 15% by reducing memory accesses.
In this study, an efficient addressing scheme for radix-4 FFT processor is presented. The proposed method uses extra registers to buffer and reorder the data inputs of the butterfly unit. It avoids the modulo-r addition in the address generation; hence, the critical path is significantly shorter than the conventional radix-4 FFT implementations. A significant property of the proposed method is that the critical path of the address generator is independent from the FFT transform length N, making it extremely efficient for large FFT transforms. For performance evaluation, the new FFT architecture has been implemented by FPGA (Altera Stratix) hardware and also synthesized by CMOS 0.18µm technology. The results confirm the speed and area advantages for large FFTs. Although only radix-4 FFT address generation is presented in the paper, it can be used for higher radix FFT.
Ultrasonic detection and characterization of targets concealed by scattering noise is remarkably challenging. In this study, a neural network (NN) coupled to split-spectrum processing (SSP) is examined for target echo visibility enhancement using experimental measurements with input signal-to-noise ratio around 0 dB. The SSP-NN target detection system is trainable and consequently is capable of improving the target-to-clutter ratio by an average of 40 dB. The proposed system is exceptionally robust and outperforms the conventional techniques such as minimum, median, average, geometric mean, and polarity threshold detectors. For realtime imaging applications, a field-programmable gate array (FPGA)-based hardware platform is designed for system-onchip (SoC) realization of the SSP-NN target detection system. This platform is a hardware/software co-design system using parallel and pipelined multiplications and additions for highspeed operation and high computational throughput.
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