Radix-8 FFT processor design based on FPGA

Sun, Mingjun; Tian, Lei; Dai, Dongmin

doi:10.1109/cisp.2012.6469786

Cited by 10 publications

(6 citation statements)

References 14 publications

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“…This FFT processor is in Modelsim (Verilog coding). X 1 (k) and X 2 (k) are then supplied to SNR module in Modelsim for error calculation, based on equation (1). Pnoise or error calculation e(k) can be calculate using Equation 6.…”

Section: Signal-to-noise Modulementioning

confidence: 99%

“…Radix-8 have the highest average SNR value compared to the rest. Higher SNR indicates better signal accuracy [1], [7], [12].…”

Section: Signal-to-noise Ratiomentioning

confidence: 99%

“…While FFT is the resulting algorithm from exploitation of DFT symmetry and periodicity characteristic. FFT reduced the complexity and computational requirement of the DFT from N 2 to N log 2 N, based on Cooley-Turkey algorithm [1]. Shown in Equation 1 is the FFT implementation to compute the complex DFT, where N is number of FFT point and k = 0,1,2, … ,N-1.…”

Section: Introductionmentioning

confidence: 99%

“…This paper studied SNR on pipelined FFT processor. Three types of pipelined FFT discsuss in this paper are radix-8 [1], [8], [9], radix-4 single-path delay feedback (R4SDF) [7], [9], [10] and radix-4 singlepath delay commutator (R4SDC) [9], [11].…”

Section: Introductionmentioning

confidence: 99%

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Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor

et al. 2018

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Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-to-noise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.

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Section: Signal-to-noise Modulementioning

confidence: 99%

“…Radix-8 have the highest average SNR value compared to the rest. Higher SNR indicates better signal accuracy [1], [7], [12].…”

Section: Signal-to-noise Ratiomentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor

et al. 2018

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“…The work presented in [1] presents a formal verification methodology where the system accuracy is verified algebraically. The work presented in [2] is focused in the implementation of an FFT core, but also verification is made with a few trivial test cases that do not provide high confidence about its correctness. In [3] the system architecture is analyzed to estimate its accuracy.…”

Section: Introductionmentioning

confidence: 99%

Functional verification for FFT cores

Pachiana

Rodriguez

Paolini

2014

2014 Argentine Conference on Micro-Nanoelectronics, Technology and Applications (EAMTA)

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This paper presents an initial approach to the development of a component for black box functional verification of FFT cores. First, a coverage model based on equivalence partitioning and boundary value analysis of the input signal space is defined, allowing to identify a set of test cases of interest. Then, the design and implementation of a SystemVerilog testbench is described and employed to stimulate three FFT IPs, performing a coverage driven verification procedure for checking performance, configurations and accuracy correctness.

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Designing of FPGA based high performance 32 bit FFT processor with BIST

Tathode

Jassutkar

2014

2014 International Conference on Communication and Signal Processing

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Radix-8 FFT processor design based on FPGA

Cited by 10 publications

References 14 publications

Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor

Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor

Functional verification for FFT cores

Designing of FPGA based high performance 32 bit FFT processor with BIST

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