Functional verification for FFT cores

Abstract

This paper presents an initial approach to the development of a component for black box functional verification of FFT cores. First, a coverage model based on equivalence partitioning and boundary value analysis of the input signal space is defined, allowing to identify a set of test cases of interest. Then, the design and implementation of a SystemVerilog testbench is described and employed to stimulate three FFT IPs, performing a coverage driven verification procedure for checking performance, configurations and accuracy correctness.