Abstract:Synthesis and optimization of quantum circuits have received significant attention from researchers in recent years. Developments in the physical realization of qubits in quantum computing have led to new physical constraints to be addressed. One of the most important constraints that is considered by many researchers is the nearest neighbor constraint which limits the interaction distance between qubits for quantum gate operations. Various works have been reported in the literature that deal with nearest neig… Show more
“…Experimental results shown in Table 3 are in agreement with previously published NN higher-dimensional optimization works [17,18,20,32,34,36] on the advantage granted by higher-dimensional topologies. The NN restriction becomes less restrictive as the number of dimensions increases, translating into a lower number of additional SWAP gates required for the NN conversion.…”
Section: Experimental Results and Analysissupporting
confidence: 89%
“…The NN restriction becomes less restrictive as the number of dimensions increases, translating into a lower number of additional SWAP gates required for the NN conversion. Presented results also confirm that the two optimization objectives are in compromise (improving f 1 may deteriorate f 2 and vice versa), as predicted by Lye et al [20] and experimentally supported by Ruffinelli and Barán [32]. Converted 3DSL circuits provide an average SWAP insertion reduction of 40.6% over converted 1DSL circuits.…”
Section: Experimental Results and Analysissupporting
confidence: 85%
“…Lye et al [20] present the first exact NN conversion method for two-dimensional grids based on Pseudo-Boolean Optimization (PBO). This method is not scalable, but serves as a performance benchmark of heuristic methods for smaller circuits.…”
The Nearest Neighbor (NN) restriction in quantum circuits requires quantum gates to act on geometrically adjacent qubits. Methods that convert generic quantum circuits and allow them to comply with the NN restriction have already been studied in the literature, where the main technique to accomplishing this task is by inserting SWAP gates into the circuit. In previous works, other authors have introduced a two-dimensional multi-objective NN conversion algorithm that takes into account two simultaneous objectives: the minimization of the two-dimensional grid size and the minimization of the number of SWAP gates required to allow any generic circuit to comply with the NN restriction. An extended higher-dimensional version of these previous methods is presented in this work, maintaining the same optimization objectives. We present experimental results for three-dimensional circuits, which show improvements for 52.6% of the tested circuits over all previously published results to date.
“…Experimental results shown in Table 3 are in agreement with previously published NN higher-dimensional optimization works [17,18,20,32,34,36] on the advantage granted by higher-dimensional topologies. The NN restriction becomes less restrictive as the number of dimensions increases, translating into a lower number of additional SWAP gates required for the NN conversion.…”
Section: Experimental Results and Analysissupporting
confidence: 89%
“…The NN restriction becomes less restrictive as the number of dimensions increases, translating into a lower number of additional SWAP gates required for the NN conversion. Presented results also confirm that the two optimization objectives are in compromise (improving f 1 may deteriorate f 2 and vice versa), as predicted by Lye et al [20] and experimentally supported by Ruffinelli and Barán [32]. Converted 3DSL circuits provide an average SWAP insertion reduction of 40.6% over converted 1DSL circuits.…”
Section: Experimental Results and Analysissupporting
confidence: 85%
“…Lye et al [20] present the first exact NN conversion method for two-dimensional grids based on Pseudo-Boolean Optimization (PBO). This method is not scalable, but serves as a performance benchmark of heuristic methods for smaller circuits.…”
The Nearest Neighbor (NN) restriction in quantum circuits requires quantum gates to act on geometrically adjacent qubits. Methods that convert generic quantum circuits and allow them to comply with the NN restriction have already been studied in the literature, where the main technique to accomplishing this task is by inserting SWAP gates into the circuit. In previous works, other authors have introduced a two-dimensional multi-objective NN conversion algorithm that takes into account two simultaneous objectives: the minimization of the two-dimensional grid size and the minimization of the number of SWAP gates required to allow any generic circuit to comply with the NN restriction. An extended higher-dimensional version of these previous methods is presented in this work, maintaining the same optimization objectives. We present experimental results for three-dimensional circuits, which show improvements for 52.6% of the tested circuits over all previously published results to date.
“…More connectivity will enable more two-qubit interactions. However, there is also a physical limitation for the maximum nearest neighbour interactions a qubit can sustain [57].…”
We propose a hypercube switching architecture for the perfect state transfer (PST) where we prove that it is always possible to find an induced hypercube in any given hypercube of any dimension such that PST can be performed between any two given vertices of the original hypercube. We then generalise this switching scheme over arbitrary number of qubits where also this routing feature of PST between any two vertices is possible. It is shown that this is optimal and scalable architecture for quantum computing with the feature of routing. This allows for a scalable and growing network of qubits. We demonstrate this switching scheme to be experimentally realizable using superconducting transmon qubits with tunable couplings. We also propose a PST assisted quantum computing model where we show the computational advantage of using PST against the conventional resource expensive quantum swap gates. In addition, we present the numerical study of signed graphs under Corona product of graphs and show few examples where PST is established, in contrast to pre-existing results in the literature for disproof of PST under Corona product. We also report an error in pre-existing research for qudit state transfer over Bosonic Hamiltonian where unitarity is violated.
“…Furthermore, local reordering strategy is performed by considering all possible paths between interacting qubits. In [32], authors extended their previous method presented in [30] to be applied on 3D grid circuits. Qubits' assignment and the consequent SWAP gate insertion are performed on a block-byblock basis to reduce the number of SWAP gates.…”
In some quantum technologies, an interaction is only allowed between physically adjacent qubits, hence the nearest-neighbor requirement is needed. In such technologies, quantum gates are limited to operate on adjacent qubits. To make a quantum circuit compliant with the nearest-neighbor requirement, SWAP gates are inserted into the circuit to move the interacting qubits of a gate to be adjacent to each other. The mapping of qubits on the physical environment has an important role on reducing the number of SWAP gates and thus the circuit latency. Focusing on this issue, in this paper, a method is proposed that maps a quantum circuit onto a 3D physical hardware such as a 3D optical lattice. A new methodology for this mapping problem is proposed based on a complex network spectral clustering algorithm and graph theory, which are suitable for very large scale networks. It includes three steps: finding the order of qubit mapping, placing physical qubits, and routing. Simulation results show that the proposed mapping approach not only decreases the average number of SWAP gates by about 37% but also improves the average runtime by about 87% for the 2D architecture compared to PAQCS. Moreover, it reduces the average number of SWAP gates for the 3D architecture by 17.1% compared to the best studies in the literatures.
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