Efficient computation of buffer capacities for cyclo-static dataflow graphs

Wiggers, Maarten H.; Bekooij, Marco; Smit, Gerard J. M.

doi:10.1145/1278480.1278647

Cited by 61 publications

(39 citation statements)

References 9 publications

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“…The following SDFGs are extracted from realistic applications: modem [1], sample-rate converter [1], satellite receiver [18], mp3playback [19], channel equalizer [20], H.263 decoder [10], H.263 encoder [21], and MP3 decoder [10]. We also consider the bipartite SDFG [18] which is a commonly used artificial SDFG.…”

Section: Resultsmentioning

confidence: 99%

Modeling static-order schedules in synchronous dataflow graphs

Damavandpeyma

Stuijk

Basten

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-Synchronous dataflow graphs (SDFGs) are used extensively to model streaming applications. An SDFG can be extended with scheduling decisions, allowing SDFG analysis to obtain properties like throughput or buffer sizes for the scheduled graphs. Analysis times depend strongly on the size of the SDFG. SDFGs can be statically scheduled using static-order schedules. The only generally applicable technique to model a staticorder schedule in an SDFG is to convert it to a homogeneous SDFG (HSDFG). This conversion may lead to an exponential increase in the size of the graph and to sub-optimal analysis results (e.g., for buffer sizes in multi-processors). We present a technique to model periodic static-order schedules directly in an SDFG. Experiments show that our technique produces more compact graphs compared to the technique that relies on a conversion to an HSDFG. This results in reduced analysis times for performance properties and tighter resource requirements.

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Section: Resultsmentioning

confidence: 99%

Modeling static-order schedules in synchronous dataflow graphs

Damavandpeyma

Stuijk

Basten

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…In the design of pipelined applications, design space exploration techniques are usually required since the design solution space, even for relatively small applications, can be very huge because of the several elements which compose each solution (i.e., the mapping and the pipeline stage assignment of each actor, the schedule on each processing element). Left part of Table I reports the size of the design solution space of stage assignment problem for some common SDF benchmarks (modem [12], sample-rate converter [12], satellite receiver [13], mp3playback [14], H263 decoder [15], H263 encoder [16] and MP3 decoder [15]). Note that, even considering only the pipeline stage assignment problem, the solution design space can be quite large even on simple applications.…”

Section: Complexity Of the Proposed Methodologymentioning

confidence: 99%

“…Since the ordering of the actor activations which compose a PSOS is absolute, this can be described by simply specifying the order between each pair of activations: all the other relative orderings will be implied by these. DSM forces the actor of choice of a decision state to be executed before all the other active actors, but to guarantee the satisfaction of the required schedule it is sufficient to impose that in each decision state the actor of choice is executed before the actor which follows it in the schedule (lines [8][9][10][11][12][13][14][15][16][17][18][19]). This optimization, like the ones proposed in [2], aims at reducing the size of the produced graph, but since they are not equivalent, they have all to be applied in order to produce the smallest graph.…”

Section: A Modeling Of Mapping and Schedulingmentioning

confidence: 99%

Modeling pipelined application with Synchronous Data Flow graphs

Lattuada

Ferrandi

2013

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

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Abstract-Streaming applications can efficiently exploit multiprocessors architectures by means of pipelined parallelism, but designing this type of applications can be an hard task. Different subproblems have indeed to be solved: partitioning, mapping, scheduling and pipeline stage assignment. For this reason, high level abstraction models are adopted during design flow since they simplify this process by hiding most of the architectural details. Synchronous Data Flow (SDF) graphs, widely adopted to describe streaming applications, naturally model only their partitioning, so they usually have to be integrated with other types of representations.In this paper Pipelined Application Modeling (PAM), a methodology to create a Synchronous Data Flow graph describing all the aspects of a pipelined application, is presented. The methodology starts from the SDF graph describing the partitioning of the application and enriches it with new actors and channels detailing the mapping, the scheduling and the pipeline stage assignment of the considered solution. The obtained SDF graph, describing all the aspects of the solution in a formal and compact way, facilitates the evaluation of different solutions during design space exploration.

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“…Data flow models of computation allow for efficient determination of system throughput [8] and required buffer sizes [9], [10]. However, these approaches restrict to one-dimensional streams of data whereas image processing applications communicate multi-dimensional image arrays.…”

Section: Problem Formulation and Related Workmentioning

confidence: 99%

“…Instead, a self-timed schedule is deployed in which the actor invocations are controlled by the availability of input data and free output space. The property of monotonic execution for data flow graphs [9] guarantees that no deadlock occurs and that the throughput attains at least the value determined during analysis.…”

Section: Buffer Analysismentioning

confidence: 99%

Model-based synthesis and optimization of static multi-rate image processing algorithms

Keinert

Dutta

Hannig

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special purpose architectures in form of FPGAs or ASICs. However, their efficient implementation is still a challenge, as the design complexity causes exploding development times and costs. This paper presents a new design flow which permits to specify, analyze, and synthesize complex image processing algorithms. A novel buffer requirement analysis allows exploiting possible tradeoffs between required communication memory and computational logic for multi-rate applications. The derived schedule and buffer results are taken into account for resource optimized synthesis of the required hardware accelerators. Application to a multi-resolution filter shows that buffer analysis is possible in less than one second and that scheduling alternatives influence the required communication memory by up to 24% and the computational resources by up to 16%. I. INTRODUCTIONAs design complexity is becoming a major barrier for technical progress because of expensive and error-prone development, new design methodologies raising the level of abstraction are becoming increasingly popular. Simulink [1] or SystemC based high-level synthesis [2] tools for instance permit to compose complex systems by communicating blocks. However, these approaches do not allow for system-level analysis like determination of required communication buffer sizes, as the blocks can contain arbitrarily complex operations. Alternative approaches like [3], [4] are restricted to a subset of sequential languages like C. However, extraction of the contained parallelism is challenging, especially as analysis on individual statements can get computationally expensive [5].In order to address these aspects, this paper presents a novel design flow for high-level synthesis of complex multi-rate image processing applications containing up-and downsamplers. It extends existing previous work by usage of latticebased buffer analysis which considers different scheduling alternatives for multi-rate systems. As the obtained results are directly taken into account during hardware synthesis, we are able to exploit tradeoffs between required communication memory and computational logic. Furthermore, in contrast to many other approaches, analysis of the overall system does not rely on solving Integer Linear Programs (ILPs) in case of acyclic problems. Instead ILPs are only required for local analysis like actor synthesis or dependency calculation in order to assure good scaling properties of our design flow.

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Efficient computation of buffer capacities for cyclo-static dataflow graphs

Cited by 61 publications

References 9 publications

Modeling static-order schedules in synchronous dataflow graphs

Modeling static-order schedules in synchronous dataflow graphs

Modeling pipelined application with Synchronous Data Flow graphs

Model-based synthesis and optimization of static multi-rate image processing algorithms

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