Modeling pipelined application with Synchronous Data Flow graphs

Lattuada, Marco; Ferrandi, Fabrizio

doi:10.1109/samos.2013.6621105

Cited by 4 publications

(2 citation statements)

References 19 publications

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“…Since our work in this paper has little to do with buffer requirements, we ignore the details here. In various works, the methods used to handle throughput are quite similar to traditional throughput analysis; however some of them present novel approaches to handle throughput, such as the pipeline scheduling in [13] and [14].…”

Section: Preliminaries On Dvfs and Sdfmentioning

confidence: 99%

Energy-Aware Scheduling for Acyclic Synchronous Data Flows on Multiprocessors

2013

J. Inter. Net.

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Synchronous Data Flow (SDF) is a useful computational model in image processing, computer vision, and DSP. Previously, throughput and buffer requirement analyses have been studied for SDFs. In this paper, we address energy-aware scheduling for acyclic SDFs on multiprocessors. The multiprocessor considered here has the capability of Dynamic Voltage and Frequency Scaling (DVFS), which allows processors to operate at different power/energy levels to reduce the energy consumption. An acyclic SDF graph can first be transformed to an equivalent homogeneous SDF graph and then to a Directed Acyclic Graph (DAG) for one iteration of it. We propose pipeline scheduling to address two closely related problems. The first problem is minimizing energy consumption per iteration of the acyclic SDF given a throughput constraint; the second problem is maximizing throughput given an energy consumption constraint per iteration of the acyclic SDF. Since the space of valid total orders of the transformed DAG is exponential, and finding the optimal order is no easy task, we first derive a valid total order, which can be achieved via various strategies, based on the DAG. Given the derived order, we design two dynamic programming algorithms, which produce optimal pipeline scheduling (including pipeline stage partitioning and the frequency setting for each stage), for the two problems, respectively. We also compare the performances of using various strategies to derive a valid total order. Analyses, experiments, and simulations demonstrate the strength of our proposed pipeline scheduling and dynamic programming algorithms.

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Section: Preliminaries On Dvfs and Sdfmentioning

confidence: 99%

Energy-Aware Scheduling for Acyclic Synchronous Data Flows on Multiprocessors

2013

J. Inter. Net.

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“…All these aspects can only be analysed after non-trivial graph transformations (as e.g. exemplified in [16]).…”

Section: Introductionmentioning

confidence: 99%

Optimising Multiprocessor Image-Based Control Through Pipelining and Parallelism

Mohamed

Goswami

et al. 2021

IEEE Access

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Image-based control (IBC) systems have a long sensing delay due to compute-intensive image processing. Modern multiprocessor IBC implementations consider either parallelisation of the sensing task or pipelining of the control loop to cope with this long delay. However, the impact of both parallelisation and pipelining together on the quality-of-control (QoC) of IBC systems is not explored in the literature. We present a model-based design method for multiprocessor IBC implementation, considering both parallelisation and pipelining together. In particular, we address the following problem: For a given platform allocation, what is the optimal degree of pipelining and degree of parallelisation required to maximise the QoC? The proposed method takes into account image-workload variations, inter-frame dependencies and platform constraints. The application is efficiently modelled and analysed using a scenario-aware dataflow graph, and an implementation-aware switched controller is designed that optimises QoC and guarantees stability. We validate the proposed method using simulations and hardware-in-the-loop experiments, considering a lane-keeping assist system.INDEX TERMS image-based control, switched linear control, scenario-based design, platform-aware design, multiprocessor implementation, hardware-in-the-loop validation

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Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs

Lattuada

Ferrandi

2014

J Sign Process Syst

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Synchronous Data Flow graphs are widely adopted in the designing of streaming applications, but were originally formulated to describe only how an application is partitioned and which data are exchanged among different tasks. Since Synchronous Data Flow graphs are often used to describe and evaluate complete design solutions, missing information (e.g., mapping, scheduling, etc.) has to be included in them by means of further actors and channels to obtain accurate evaluations. To address this issue preserving the simplicity of the representation, techniques that model data transfer delays by means of ad-hoc actors have been proposed, but they model independently each communication ignoring contentions. Moreover, they do not usually consider at all delays due to buffer contentions, potentially overestimating the throughput of a design solution.In this paper a technique to extend Synchronous Data Flow graphs by adding ad-hoc actors and channels to model resolution of resources contentions is proposed. The results show that the number of added actors and channels is limited but that they can significantly increase the Synchronous Data Flow graph accuracy.

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Modeling pipelined application with Synchronous Data Flow graphs

Cited by 4 publications

References 19 publications

Energy-Aware Scheduling for Acyclic Synchronous Data Flows on Multiprocessors

Energy-Aware Scheduling for Acyclic Synchronous Data Flows on Multiprocessors

Optimising Multiprocessor Image-Based Control Through Pipelining and Parallelism

Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs

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