Efficient backtracking instruction schedulers

Abstract

Current schedulers for acyclic regions schedule operations in dependence order and never revisit or undo a scheduling decision on any operation. In contrast, backtracking schedulers may unschedule already scheduled operations, in order to make space for the operation currently being scheduled. Backtracking schedulers have the potential for generating better schedules, e.g. more effectively filling branch delay slots, but are more compile-time intensive and therefore, not considered practical for production use.In this report, we first describe conventional cycle and list schedulers followed by two novel backtracking schedulers. The full-backtracking OperBT scheduler enables backtracking for all operations and unschedules already scheduled operations to make space for the current operation, if, among other situations, there is no available slot that satisfies dependence constraints. This scheduler is effective in generating high quality schedules that for instance, successfully fill branch delay slots but likely backtracks too often. The selective backtracking ListBT scheduler enables backtracking only when scheduling certain types of operations, for which backtracking is likely to be advantageous, e.g. branches. When not scheduling these operations (or operations that were displaced through backtracking), the scheduler reverts to efficient scheduling in dependence order. The ListBT scheduler backtracks less often than the OperBT scheduler. Both schedulers successfully fill a large fraction of the branch delay slots and improve performance of the scheduled code significantly.

Compiler-assisted energy optimization for clustered VLIW processors

“…The Elcor backend of the Trimaran infrastructure has a cycle scheduling algorithm designed and implemented for flat VLIW architectures [55,1]. We have modified this algorithm to perform leakage energy optimization for clustered VLIW architectures.…”

Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors

“…In the setting of the STMicroelectronics CLI-JIT compiler, we implemented Scoreboard Scheduling as described in Section 2.3 and also a Cycle Scheduling algorithm that closely follows the description of Abraham [1], including reference counting for detecting operations whose predecessors have all been scheduled. We optimized this Cycle Scheduling implementation for speed.…”

“…This implies conservative memory dependences, however we assume such a restriction is acceptable for postpass scheduling. We also merged the ReadyList and CCReadyList of [1] into a single radix-4 priority heap lexicographically ordered by lower available date and higher critical path priority.…”

“…Such media processing software can be compiled to CLI byte-codes thanks to the Microsoft Visual Studio .NET compilers or the gcc/st/cli compiler branch contributed by STMicroelectronics [4]. This motivates Just-In-Time compilation for embedded processors like the Texas Instruments C6000 VLIW-DSP family and the STMicroelectronics ST200 VLIW-media family 1 .…”

FLASH: foresighted latency-aware scheduling heuristic for processors with customized datapaths

“…Backtracking schedulers have the potential to generate better schedules at the expense of compile-time by unscheduling operations that have been scheduled to make room for the current operation. They have been evaluated for effectively filling branch delay slots in [2]. Also, Iterative Modulo Scheduling [25], an algorithm for software pipelining innermost loops, is based on backtracking.…”