Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors

Dinechin, Benoît Dupont de

doi:10.1007/978-3-540-85451-7_40

Cited by 6 publications

(6 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Their approach uses a list-based instruction scheduler combined with a greedy register allocation (our register allocation stage shares many similarity with their work). Dupont de Dinechin [28] proposed to translate .NET bytecode into VLIW binaries, but instead use scoreboard scheduling algorithm, but only little information is provided on how register allocation is performed (the paper only suggests that the register allocation algorithm is more complex than the greedy heuristic used by Agosta).…”

Section: B Dynamic Compilationmentioning

confidence: 99%

Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW

Rokicki

Rohou²,

Derrien³

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-In order to provide dynamic adaptation of the performance/energy trade-off, systems today rely on heterogeneous multi-core architectures (different micro-architectures on a chip). These systems are limited to single-ISA approaches to enable transparent migration between the different cores. To offer more trade-off, we can integrate statically scheduled microarchitecture and use Dynamic Binary Translation (DBT) for task migration. However, in a system where performance and energy consumption are a prime concern, the translation overhead has to be kept as low as possible. In this paper we present Hybrid-DBT, an open-source, hardware accelerated DBT system targeting VLIW cores. Three different hardware accelerators have been designed to speed-up critical steps of the translation process. Experimental study shows that the accelerated steps are two orders of magnitude faster than their software equivalent. The impact on the total execution time of applications and the quality of generated binaries are also measured.

show abstract

Section: B Dynamic Compilationmentioning

confidence: 99%

Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW

Rokicki

Rohou²,

Derrien³

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…We already mentioned NVidia's Denver architecture [5] and Transmeta CMS [4] which are completely closed. There is also the works from Dinechin and the one of Agosta et al who developed Just-in-time compilers targeting VLIW [9], [10]. However, these tools are based on a bytecode (Java bytecode or CLI) and we favored the idea of single-ISA systems.…”

Section: Related Workmentioning

confidence: 99%

Supporting runtime reconfigurable VLIWs cores through dynamic binary translation

Rokicki

Rohou

Derrien

2018

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

Abstract-Single ISA-Heterogeneous multi-cores such as the ARM big.LITTLE have proven to be an attractive solution to explore different energy/performance trade-offs. Such architectures combine Out of Order cores with smaller in-order ones to offer different power/energy profiles. They however do not really exploit the characteristics of workloads (compute-intensive vs. control dominated). In this work, we propose to enrich these architectures with runtime configurable VLIW cores, which are very efficient at compute-intensive kernels. To preserve the single ISA programming model, we resort to Dynamic Binary Translation, and use this technique to enable dynamic code specialization for Runtime Reconfigurable VLIWs cores. Our proposed DBT framework targets the RISC-V ISA, for which both OoO and in-order implementations exist. Our experimental results show that our approach can lead to best-case performance and energy efficiency when compared against static VLIW configurations.

show abstract

“…This compiler was directly connected to the STMicroelectronics JIT compiler for CLI [9], which implements the out-of-SSA techniques proposed in this paper, the techniques of Sreedhar et al [3], and also the fast liveness checking for SSA [16]. This experimental setup ensures that algorithms are implemented in the context of a real JIT compiler, yet the code they process is highly optimized C code.…”

Section: E Qualitative Experimentsmentioning

confidence: 99%

“…Register allocation often relies on "linear scan" techniques [5], [6], [7], [8] in order to save compilation time and space by avoiding interference graphs. Similarly, instruction scheduling is usually reduced to postpass scheduling [9]. Pre-pass scheduling is applied only where predicted or found beneficial [10], [11].…”

mentioning

confidence: 99%

Revisiting Out-of-SSA Translation for Correctness, Code Quality and Efficiency

Boissinot

Darte

Rastello

et al. 2009

2009 International Symposium on Code Generation and Optimization

View full text Add to dashboard Cite

Abstract-Static single assignment (SSA) form is an intermediate program representation in which many code optimizations can be performed with fast and easy-to-implement algorithms. However, some of these optimizations create situations where the SSA variables arising from the same original variable now have overlapping live ranges. This complicates the translation out of SSA code into standard code. There are three issues to consider: correctness, code quality (elimination of copies), and algorithm efficiency (speed and memory footprint). Briggs et al. proposed patches to correct the initial approach of Cytron et al. A cleaner and more general approach was proposed by Sreedhar et al., along with techniques to reduce the number of generated copies. We propose a new approach based on coalescing and a precise view of interferences, in which correctness and optimizations are separated. Our approach is provably correct and simpler to implement, with no patches or particular cases as in previous solutions, while reducing the number of generated copies. Also, experiments with SPEC CINT2000 show that it is 2x faster and 10x less memory-consuming than the Method III of Sreedhar et al., which makes it suitable for just-in-time compilation.

show abstract

Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors

Cited by 6 publications

References 16 publications

Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW

Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW

Supporting runtime reconfigurable VLIWs cores through dynamic binary translation

Revisiting Out-of-SSA Translation for Correctness, Code Quality and Efficiency

Contact Info

Product

Resources

About