FLASH: foresighted latency-aware scheduling heuristic for processors with customized datapaths

Kudlur, M.; Fan, K.; Chu, M.; Ravindran, R.; Clark, N.; Mahlke, S.

doi:10.1109/cgo.2004.1281675

Cited by 2 publications

(2 citation statements)

References 28 publications

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“…In the past, there have been several studies to use only selected forwarding paths such that impact on performance is minimal [Fan et al 2003;Shrivastava et al 2005], and compiler techniques were suggested to further minimize the impact on performance [Park et al 2006;Kudlur et al 2004]. As less frequently used paths are not present in the limited bypass case, there will be minimal effect on RF energy savings achieved due to our proposed architecture.…”

Section: Previous Workmentioning

confidence: 96%

Shared-port register file architecture for low-energy VLIW processors

Goel

Kumar

Panda

2014

ACM Trans. Archit. Code Optim.

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We propose a reduced-port Register File (RF) architecture for reducing RF energy in a VLIW processor. With port reduction, RF ports need to be shared among Function Units (FUs), which may lead to access conflicts, and thus, reduced performance. Our solution includes (i) a carefully designed RF-FU interconnection network that permits port sharing with minimum conflicts and without any delay/energy overheads, and (ii) a novel scheduling and binding algorithm that reduces the performance penalty. With our solution, we observed as much as 83% RF energy savings with no more than a 10% loss in performance for a set of Mediabench and Mibench benchmarks.

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Section: Previous Workmentioning

confidence: 96%

Shared-port register file architecture for low-energy VLIW processors

Goel

Kumar

Panda

2014

ACM Trans. Archit. Code Optim.

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“…However, this is generally done in the context of a single-issue architecture, thus there is no significant scheduling component. A related area is scheduling to processors with partial register bypass networks [11,23]. Partial bypass introduces the problem of variable latencies on dataflow edges depending on function units chosen for a producer/consumer pair.…”

Section: Related Workmentioning

confidence: 99%

Modulo scheduling for highly customized datapaths to increase hardware reusability

Fan

Park

Kudlur

et al. 2008

Proceedings of the 6th Annual IEEE/ACM International Symposium on Code Generation and Optimization

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In the embedded domain, custom hardware in the form of ASICs is often used to implement critical parts of applications when performance and energy efficiency goals cannot be met with software implementations on a general purpose processor or DSP. The downsides of using ASICs include high non-recurring engineering costs, inability to accommodate changes in the application after production, and inability to reuse hardware for new applications. However, by allowing a degree of post-programmability, the hardware can retain high performance and energy efficiency while increasing flexibility and reusability. The difficulty with programmable custom hardware lies in mapping new applications onto an existing datapath that is both sparse and irregular. This paper proposes a constraint-driven modulo scheduler that maps softwarepipelineable loops onto programmable loop accelerator hardware. The scheduler is able to target accelerators with widely varying levels of datapath functional capability and connectivity, and thus, varying degrees of programmability. The paper investigates the ability of the scheduler to map new loops onto existing hardware, which depends on both the degree of programmability of the hardware as well as the similarity of the new loop to the original loop for which the hardware was designed.

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FLASH: foresighted latency-aware scheduling heuristic for processors with customized datapaths

Abstract: Application-specific instruction set processors (ASIPs)

Cited by 2 publications

References 28 publications

Shared-port register file architecture for low-energy VLIW processors

Shared-port register file architecture for low-energy VLIW processors

Modulo scheduling for highly customized datapaths to increase hardware reusability

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