Efficient Analog Circuit Modeling By Boolean Logic Operations

Abstract

In this paper, we propose a novel symbolic analysis method for analog behavioral modeling by Boolean logic operations and graph representation. The exact symbolic analysis problem is formulated as a logic circuit synthesis problem where we build a logic circuit which detects whether or not a given symbolic term is a valid product term from a determinant. The logic circuit is represented by binary decision diagrams (BDDs), which can be trivially transformed into zero-suppressed binary decision diagrams(ZBDDs). ZBDDs are essentially determinant decision diagrams (DDDs) representation of a determinant. The significance of the new method is that all product terms can be constructed implicitly and simultaneously, in contrast to all previous symbolic analysis methods where symbolic terms are generated explicitly and sequentially by Laplace expansion or topological methods. We further apply the logic synthesis idea to generating symbolic coefficients of s-expanded polynomials and present a method to compute coefficients individually and selectively. Our new approach demonstrates an inherent relationship between circuit simulation and logic synthesis for the first time. Experimental results show the speedup of our new method over the existing flat method and its greater capacity over both existing flat and hierarchical symbolic analyzers.