Efficiency of SOI-Like Structures for Reducing the Thermal Resistance in Thin-Film SOI Power LDMOSFETs

Roig, J.; Urresti, J.; Cortés, I.; Flores, D.; Hidalgo, S.; Millán, José del R.

doi:10.1109/led.2004.837580

Cited by 8 publications

(11 citation statements)

References 11 publications

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“…The problem is exacerbated by the required thicker BOX in analog and mixed-signal applications than in digital CMOS to reduce noise coupling [111][112][113]. Techniques to reduce the thermal resistance in SOI-like substrates are described in [114,115].…”

Section: Self-heating and Temperature Effectsmentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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This chapter focuses mainly on the drain-extended MOS transistor, DEMOS, for high voltage applications, and on the lateral double-diffused MOS transistor, LDMOS, for high power applications. In both cases, the drain is extended with a lightly-doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface-field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation, body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications. IntroductionThe MOSFETs discussed in Chap. 6 are designed for digital, analog, mixed-signal, and RF applications that operate in the low-to-medium voltage range of about 0.8-6 V. Many analog applications, however, require transistors that can handle voltages above 20 V and currents in the ampere range. Those transistors are referred to as high-voltage and power transistors. This chapter provides a comprehensive analysis of the drain-extended MOS transistor (DEMOS), for high-voltage and low-current applications, and the lateral double-diffused MOS (LDMOS) transistor, LDMOS, for power applications. (The "D" in LDMOS describes the sequential (double) diffusion of boron and arsenic through the same oxide opening, defining a precise channel length (Chap. 9). The "L" means that the current path is parallel to the silicon surface (lateral), as opposed to "V" in VDMOS where the current is nearly vertical to the silicon surface.) Schematic cross sections of both transistors (Table 7.1). The DEMOS is typically processed without added process complexity, whereas the LDMOS requires optimization of the P-body and N-drift regions to achieve high voltages and currents while minimizing the drain-to-source resistance and transistor area.The interest in bipolar, CMOS, and DMOS (BCD) technologies has been driven primarily by the proliferation of portable electronics, automotive electronics, and the need for energy efficiency. These applications cluster around different operating points, with 24 V for portable electronics; 60 V for automotive, solar, and LED backlighting; 85 V for power over Ethernet; 120 V for telecommunication; and 700 V for offline LED lighting, consumer, and industrial applications. As a result, BCD is now the technology of choice to realize power ICs by most integrated device manufacturers (IDM) and foundries [1][2][3][4][5].This chapter focuses mainly on transistors with voltage capabilities in the range of 20-700 V, where the bulk of the product applications lie.

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Section: Self-heating and Temperature Effectsmentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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“…Fig. 1 illustrates a 190 V Si/SiC LDMOS and an equivalent structure modularised for the SOI, PSOI and PSOSiC, created in SILVACO according to [6][7][8]. The interface charges of Si/SiO2 and Si/SiC are set to +4×10 10 cm -2 [9] and -2×10 10 cm -2 [10], respectively.…”

Section: Introductionmentioning

confidence: 99%

“…This positioning of an opening in the PSOI and PSOSiC minimises the effect of the interrupted buried oxide (BOX) on the SOI RESURF in the transistors and prevents the formation of P-N RESURF mentioned by [5], in a way that a fair comparison among the devices can be achieved. This also reduces the difficulty in fabricating such LDMOSFETs, as the thermally conductive region can be engineered after the wafer bonding processes [7,8]. However, doing so requires extra chip area [7], unlike the PSOI type having an opening right underneath the active region [5].…”

Section: Introductionmentioning

confidence: 99%

Numerical Study of Energy Capability of Si/SiC LDMOSFETs

Chan

Mawby

et al. 2017

MSF

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Abstract. A comparable study is made on the energy capability of 190 V LDMOSFETs in Si/SiC, SOI, PSOI and PSOSiC technology, using capacitive and inductive switching circuits established in SILVACO Mixed-mode simulators. The results show that the PSOSiC has a thermal advantage compared with other SOI structures under a 48-µs-power-pulse condition, but the Si/SiC device offers superior cooling and energy handling ability in all switching cases despite having a larger chip area.

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“…Ενδεικτικά, αναφέρονται μερικά ακόμη από τα πλεονεκτήματα που χαρακτηρίζουν τις διατάξεις SeOI συγκρινόμενες με τα συμβατικά κυκλώματα CMOS. Η θερμική τους αντίσταση εμφανίζεται μειωμένη γεγονός που οδηγεί στην αύξηση της αποδοτικότητας τους [110]. Επιπλέον, καθίστανται χρήσιμες για εφαρμογές σχετικές με το διάστημα επειδή δεν υποβιβάζονται τα χαρακτηριστικά τους όταν εκτίθενται σε ακτινοβολία.…”

Section: διαγωγιμότητα (Transconductance)unclassified

“…Τέλος, στο εσωτερικό των νησίδων παρατηρούνται δομικές ατέλειες ενώ εμφανίζονται δύο περιοχές με διαφορετικούς κρυσταλλογραφικούς προσανατολισμούς (διδυμία). Στην ένθετη φωτογραφία του σχήματος 2.6.4 απεικονίζεται το αντίστοιχο φάσμα περίθλασης ως προς τον άξονα [110], το οποίο περιέχει τους κροσσούς περίθλασης του υποστρώματος Si και των ανεπτυγμένων στρωμάτων Υ2Ο3 και Si. Οι κροσσοί με μεγαλύτερη ένταση αντιστοιχούν στο υπόστρωμα.…”

Section: η μικροσκοπία ηλεκτρονίων διέλευσης (Transmission Electronunclassified

Νέα Υλικά Για Το Διηλεκτρικό Πύλης Σε Τρανζίστορ Προηγμένης Τεχνολογίας CMOS

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Efficiency of SOI-Like Structures for Reducing the Thermal Resistance in Thin-Film SOI Power LDMOSFETs

Cited by 8 publications

References 11 publications

High-Voltage and Power Transistors

High-Voltage and Power Transistors

Numerical Study of Energy Capability of Si/SiC LDMOSFETs

Νέα Υλικά Για Το Διηλεκτρικό Πύλης Σε Τρανζίστορ Προηγμένης Τεχνολογίας CMOS

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