“…The technique provides the ability to form high-voltage lateral devices using an inherently low-voltage IC technology [8][9][10].…”
Section: Resurf Nldmos Structurementioning
confidence: 99%
“…is the concentration which achieves maximum breakdown voltage of the structure and gives the best trade-off between the breakdown voltage and the ON-resistance. This occurs by applying the optimum RESURF'ing condition [9,10]. Figure 1 The schematic cross-section of the RESURF LDMOS.…”
Section: The Optimum Epitaxial Doping Concentration (N Epiopt )mentioning
In this paper, a RESURF high voltage (HV) nLDMOS is designed in 0.35 lm BiCMOS technology (STMicroelectronics technology-like). Optimization of the key device/process parameters of the device is performed using analytical approach and verified using advanced 2D numerical simulation. The results show excellent R ON,SP /BV trade-off (BV % 400 V and R ON,SP = 9.5 mX cm 2 for T epi = 4 lm and L Drift = 17 lm) without any added process complexity. The maximum obtained drain current is 1.8 mA/lm at a gate voltage of 5 V. The designed device is suitable for smart power integration. Ó 2014 Faculty of Engineering, Ain Shams University. Production and hosting by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
“…This makes the electric field nearly uniform in the lateral direction, which helps in increasing the maximum drain bias (V DS ) by simply increasing the length of the LDD region [24], [25]. This action is called reduced surface field (RESURF) [26], [27]. The drawback of this approach is increased resistance in the ON-state and the requirement of an additional mask [23].…”
Section: ) Lightly Doped Drain Mos (Lddmos)mentioning
Abstract-In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications. The mixed-signal performance, impact of process variations, and gate oxide reliability of these devices are compared. Lightly doped drain MOS (LDDMOS) was found to have a moderate performance advantage as compared to shallow trench isolation (STI) and non-STI drain-extended MOS (DeMOS) devices. Non-STI DeMOS devices have improved circuit performance but suffer from the worst gate oxide reliability. Incorporating an STI region underneath the gate-drain overlap improves the gate oxide reliability, although it degrades the mixed-signal characteristics of the device. The single-halo nature of DeMOS devices has been shown to be effective in suppressing the short-channel effects.Index Terms-Drain-extended MOS (DeMOS), hot carrier, input/output, lightly doped drain MOS (LDDMOS), mixed signal, reduced surface field (RESURF), reliability.
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