Effects of Rapid Thermal Annealing and Different Oxidants on the Properties of LaxAlyO Nanolaminate Films Deposited by Atomic Layer Deposition

Fei, Chenxi; Liu, Hongxia; Wang, Xing; Zhao, Lü; Zhao, Dongdong; Feng, Xingyao

doi:10.1186/s11671-017-1994-z

Cited by 4 publications

(2 citation statements)

References 29 publications

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“…It can be explained by the fact that the impurity concentration and defects decrease due to the thermal annealing supplying enough thermal energy for the by-products residing and dangling bonds decomposition and re-composition, leading to the HfO 2 /Al 2 O 3 gate stack becoming a good gate dielectric insulator. [18,19] However, as shown in Figs. 2(c) and 2(d), the density of leakage spots in sample B increases significantly after annealing, which indicates that the 087701-2 conductive paths increase significantly.…”

Section: Resultsmentioning

confidence: 89%

Improvement of the high- κ /Ge interface thermal stability using an in-situ ozone treatment characterized by conductive atomic force microscopy

Fan¹,

Cheng²,

Liu

et al. 2017

Chinese Phys. B

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In this work, an in-situ ozone treatment is carried out to improve the interface thermal stability of HfO 2 /Al 2 O 3 gate stack on germanium (Ge) substrate. The micrometer scale level of HfO 2 /Al 2 O 3 gate stack on Ge is studied using conductive atomic force microscopy (AFM) with a conductive tip. The initial results indicate that comparing with a non insitu ozone treated sample, the interface thermal stability of the sample with an in-situ ozone treatment can be substantially improved after annealing. As a result, void-free surface, low conductive spots, low leakage current density, and relative high breakdown voltage high-κ/Ge are obtained. A detailed analysis is performed to confirm the origins of the changes. All results indicate that in-situ ozone treatment is a promising method to improve the interface properties of Ge-based three-dimensional (3D) devices in future technology nodes.

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Section: Resultsmentioning

confidence: 89%

Improvement of the high- κ /Ge interface thermal stability using an in-situ ozone treatment characterized by conductive atomic force microscopy

Fan¹,

Cheng²,

Liu

et al. 2017

Chinese Phys. B

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“…SCEs [28] are influenced by both the EOT and physical gate oxide thickness, so it is essential to pay attention to both parameters in order to decrease the gate's leakage to an acceptable level. Increased attention has been paid to La 2 O 3 gate dielectrics and much research has been carried out to examine their proper functioning [29][30][31][32]. The form thickness mainly determines the structural properties of La 2 O 3 and the annealing temperature has to be well controlled to ensure the stability of the La 2 O 3 layer [33,34].…”

Section: Introductionmentioning

confidence: 99%

A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length

et al. 2021

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At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards the sub-10 nm technology node involves the complex integration of new materials (Ge, III-V, graphene) and new device architectures. To date, planar transistors still command >50% of the transistor market and applications. This work aims to downscale a planar PMOS to a 14-nm gate length using La2O3 as the high-k dielectric material. The device was virtually fabricated and electrically characterized using SILVACO. Taguchi L9 and L27 were employed to study the process parameters’ variability and interaction effects to optimize the process parameters to achieve the required output. The results obtained from simulation using the SILVACO tool show good agreement with the nominal values of PMOS threshold voltage (Vth) of −0.289 V ± 12.7% and Ioff of less than 10−7 A/µm, as projected by the International Technology Roadmap for Semiconductors (ITRS). Careful control of SiO2 formation at the Si interface and rapid annealing processing are required to achieve La2O3 thermal stability at the target equivalent oxide thickness (EOT). The effects of process variations on Vth, Ion and Ioff were investigated. The improved voltage scaling resulting from the lower Vth value is associated with the increased Ioff due to the improved drain-induced barrier lowering as the gate length decreases. The performance of the 14-nm planar bulk PMOS is comparable to the performance of the FDSOI and FinFET technologies at the same gate length. The comparisons made with ITRS, the International Roadmap for Devices and Systems (IRDS), and the simulated and experimental data show good agreement and thus prove the validity of the developed model for PMOSs. Based on the results demonstrated, planar PMOSs could be a feasible alternative to FDSOI and FinFET in balancing the trade-off between performance and cost in the 14-nm process.

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Studying the change in organic light-emitting diode performance at various vacuum-deposition rates of hole and electron transport layers

Mikaeili

Mohajerani

2020

Bull Mater Sci

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Effects of Rapid Thermal Annealing and Different Oxidants on the Properties of LaxAlyO Nanolaminate Films Deposited by Atomic Layer Deposition

Cited by 4 publications

References 29 publications

Improvement of the high- κ /Ge interface thermal stability using an in-situ ozone treatment characterized by conductive atomic force microscopy

Improvement of the high- κ /Ge interface thermal stability using an in-situ ozone treatment characterized by conductive atomic force microscopy

A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length

Studying the change in organic light-emitting diode performance at various vacuum-deposition rates of hole and electron transport layers

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