Effects of mask bias on the mask error enhancement factor (MEEF) for low k1 lithography process

Chang, Yu Ya; Wu, Yuan-Hsun; Shih, Chiang-Lin; Lin, Jengping; Kan, Francis; Lin, Jimmy

doi:10.1117/12.617212

Cited by 7 publications

(3 citation statements)

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“…The previous references report that the information of mask pattern in spatial frequency domain is limited by the cut-off frequency like equation (2) λ σ…”

Section: Lermentioning

confidence: 99%

“…In convention, the patterning resolution defined by a lithography process is roughly described by Rayleigh equation [2]. The exact resolution should be defined by simulating aerial image and considering material properties of photo resist, but k1 value can be used to describe patterning trend of each lithography technology because k1 value based on Rayleigh equation has the relation with the contrast of aerial image.…”

Section: Introductionmentioning

confidence: 99%

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Requirements of e-beam size and position accuracy for photomask of sub-32 nm HP device

et al. 2010

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As semiconductor features shrink in size and pitch, there are strong needs for an advanced mask writer which has better patterning quality. Among various requirements for next photomask writer, we have focused on the requirements of ebeam size and position accuracy for hp 32nm and beyond generation.At the era of DPT, EUV, and complex OPC, the photomask is required to have extreme control of critical dimension (CD). Based on simulation and experiment, we present the e-beam requirements for advanced mask writer, in view point of stability and accuracy. In detail, the control of e-beam size in mask writer should be decreased to 0.5nm because the size error of e-beam gives rise to large CD error according to the high complexity of mask pattern. Furthermore, the drift error of beam position should be smaller than 1nm to obtain the tight pattern placement error and to minimize the edge roughness of mask pattern for the era of computational lithography and EUV lithography.

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“…The previous references report that the information of mask pattern in spatial frequency domain is limited by the cut-off frequency like equation (2) λ σ…”

Section: Lermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Requirements of e-beam size and position accuracy for photomask of sub-32 nm HP device

et al. 2010

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“…Two nearby contacts are practically under the influence of the same scanner focus variation, so the distance between them, the PVB distance, is also a linear function of scanner focus. It has also been observed that the other two lithography parameters, exposure energy and mask manufacturing error, linearly affect the PVB widths [17], [18] and thus the PVB distance.…”

Section: Defect Probabilitymentioning

confidence: 99%

Lithography Defect Probability and Its Application to Physical Design Optimization

Shim

Chung

Shin

2017

IEEE Trans. VLSI Syst.

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Modern standard cells contain intercell margins at the left and right ends for better lithography. We introduce defect probability, which is the probability that a lithography defect occurs if the margins between two adjacent cells are missing. Computing the defect probability of all cell pairs is impractical due to lengthy lithography simulations and huge number of cell pair combinations. Two approximate methods are employed to make this computation possible: reducing the range of optical proximity correction and grouping cell pairs of similar geometry at the cell boundary. We also present how the cell layout can be modified for a lower defect probability with no impact on the cell electrical parameters. Defect probability is applied to two physical design optimization problems. In the automatic placement, we consider that all cells are initially without margins. We want to locate two cells adjacent if their defect probability is zero (or negligibly small) or insert margins in between; this is achieved using the average defect probability as one of the cost terms of the placement. Experiments in 28-nm commercial library demonstrate an 8% reduction in the area with a 4% shorter wirelength. In the second application, we assume that the standard placement using cells with margins have been performed. We want to identify redundant margins that can be removed while the defect probability is kept zero. We take a step forward and shuffle the location of a few consecutive cells in the same row so that more redundant margins are identified. Once all the redundant margins are removed, newly created whitespace is distributed to reduce routing congestion in highly congested areas. Experiments indicate a 48% reduction in the number of overflow routing grids.Index Terms-Defect probability, intercell margin, lithography defect, physical design, placement, post-placement optimization.

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A Further Analysis of the Forbidden Pitch in Photolithography in Advanced Technology Nodes

Li,

Liu,

Wang

et al. 2023

2023 IEEE 15th International Conference on ASIC (ASICON)

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Effects of mask bias on the mask error enhancement factor (MEEF) for low k1 lithography process

Cited by 7 publications

References 0 publications

Requirements of e-beam size and position accuracy for photomask of sub-32 nm HP device

Requirements of e-beam size and position accuracy for photomask of sub-32 nm HP device

Lithography Defect Probability and Its Application to Physical Design Optimization

A Further Analysis of the Forbidden Pitch in Photolithography in Advanced Technology Nodes

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