Effects of fin width on memory windows in FinFET ZRAMs

Zhang, E.X.; Fleetwood, D.M.; Alles, Michael L.; Schrimpf, R.D.; Mamouni, F. El; Xiong, Wenjing; Cristoloveanu, S.

doi:10.1016/j.sse.2010.05.012

Cited by 8 publications

(2 citation statements)

References 23 publications

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“…As shown in Figure 1, ZRAM has a few strengths compared to conventional DRAM. In addition to reduced chip size and greater process simplicity due to the absence of cell capacitor, [3] sense amplifier (S/A) to identify the data state in DRAM is not needed for ZRAM. Because it provides an opportunity for a versatile style of circuit architecture in what was originally the S/A area, it is feasible for improving the performance of ZRAM beyond the advantage of chip scaling.…”

Section: Introductionmentioning

confidence: 99%

Vertically Integrated ZRAM toward Extremely Scaled Memory

et al. 2016

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This paper discusses the demonstration of a vertically integrated gate-all-around (GAA) silicon nanowire (SiNW) channel-based dynamic random access memory (DRAM) without a cell-capacitor as a breakthrough for conventional DRAM scaling. Owing to the one-route all-dry etching process (ORADEP) with stiction-free stability and process simplicity, vertical integration of multiple silicon nanowire was achieved with high uniformity and high reproducibility. Finally, high performance suitable for further scaling was presented in zero-capacitor DRAM (ZRAM) operable with up to five-story SiNW channels without sacrificing scalability.

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Section: Introductionmentioning

confidence: 99%

Vertically Integrated ZRAM toward Extremely Scaled Memory

et al. 2016

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“…Under these circumstances, reconsidering a zero-capacitor DRAM (ZRAM) that consists of only one transistor (1T) is a timely approach. 2,3 Compared to conventional DRAM, the main advantages of the ZRAM is cell size reduction and nondestructive reading. Moreover, one of the greatest advantages of ZRAM is that there is no need to make a sense amplifier for identifying a data state.…”

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confidence: 99%

Editors' Choice—Vertically Integrated Nanowire-Based Zero-Capacitor Dynamic Random Access Memory

Lee

Kang

Ahn

et al. 2016

ECS J. Solid State Sci. Technol.

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This paper demonstrates a breakthrough for DRAM scaling: A vertically integrated gate-all-around (GAA) silicon nanowire (SiNW) channel-based dynamic random access memory (DRAM) without a cell capacitor for data storage, i.e., a zero-capacitor DRAM unlike the conventional DRAM. Vertical integration of the SiNW was attained by a one-route all-dry etching process (ORADEP), resulting in stiction-free stability and simplicity in the fabrication process. High performance that is suitable for high packing density integration is presented with vertically integrated multiple channels, which reveals a potential for an ultimate scaling of DRAM toward the end of the roadmap. With the advent of 20 nm dynamic random access memory (DRAM), 1 manufacturers of DRAM encounters the immense challenge of continuous scaling of a cell area, e.g., beyond 6F, 2 where F denotes a feature size. In particular, the cell capacitor for data storage in DRAM is a bottleneck that impedes continuous scaling. Under these circumstances, reconsidering a zero-capacitor DRAM (ZRAM) that consists of only one transistor (1T) is a timely approach.2,3 Compared to conventional DRAM, the main advantages of the ZRAM is cell size reduction and nondestructive reading. Moreover, one of the greatest advantages of ZRAM is that there is no need to make a sense amplifier for identifying a data state. This can allow a versatile core and periphery circuit architecture that enhances the device performance because the area presumably occupied by the sense amplifier is no longer needed. Additionally, high sensing current or a sensing margin (I ON /I OFF ) as large as possible is preferred for stable memory operation. In this regard, the notable increment of data sensing current based on the vertically integrated multi-stacked channels is very attractive for future DRAM technology. 4 On the other hand, short-channel effects (SCEs) have been considerably problematic in aggressive miniaturization of the transistor. 5,6 Such a trend cannot be exceptional in the scaling of a memory device. With respect to the suppression of the SCEs, a structural optimization of the transistor, i.e., multi-gated structures such as double-gate or trigate structures, have been considered as a successful approach. [7][8][9] In particular, the gate-all-around (GAA) silicon nanowire (SiNW) configuration is reportedly the most superior for suppressing I OFF due to its excellent gate controllability, 10 which enabled a demonstration of extremely scaled transistors up to sub-10 nm. 11,12 In addition, the versatile SiNW configuration itself has attracted attention for various applications.13-15 But, the extreme scaling of the SiNW inevitably sacrifices I ON due to a decrease in the cross-sectional channel area. Accordingly, an implementation of such a configuration requires a compromise between the controllability of I OFF and the drivability of I ON . 16 In this respect, a vertically integrated multi-stacked channel can recover the sacrificed I ON that occurs with the scaling of the SiNW without a sa...

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