Effects of Fin Sidewall Angle on Subthreshold Characteristics of Junctionless Multigate Transistors

Abstract

In this work, the subthreshold characteristics of a junctionless multigate transistor (JMT) with a trapezoidal fin cross section are studied by three-dimensional simulations. The effects of sidewall angle (Θ) on subthreshold swing (SS) and drain-induced barrier lowering (DIBL) are evaluated and compared with the effects of doping concentration. The results show that SS and DIBL are strongly dependent on Θ and more seriously affected by Θ variation. Meanwhile, as compared with those observed in inversion-mode multigate MOSFETs (IM-MuGFETs), the variations in SS and DIBL in JMTs with sidewall angle are better suppressed. A design guideline is finally proposed to define the optimal parameters of JMTs for a given technology.

Investigation of trench process variation on the recessed-gate junctionless MOSFETs considering the circuit application

“…θ = 60 • indicates a trench with an obvious sloped sidewall [14,16,17,22]. To meet the leakage current limitation in ITRS2015 [25], the silicon thicknesses of T si2 = 9 nm, 12 nm, and 16 nm are chosen in our simulation with correctly tuned gate work function, the same range as in [7]. The initial etch window length and channel thickness are fixed at 35 nm and 6 nm [7,16], respectively.…”

“…To meet the leakage current limitation in ITRS2015 [25], the silicon thicknesses of T si2 = 9 nm, 12 nm, and 16 nm are chosen in our simulation with correctly tuned gate work function, the same range as in [7]. The initial etch window length and channel thickness are fixed at 35 nm and 6 nm [7,16], respectively. Meanwhile, according to real RIE process, the variation of channel thickness is assumed to obey the Gaussian distribution, which is approximate to experimental data [17,22].…”

“…As an alternative, the junctionless MOSFETs (JLMs), which have uniform doping concentration and dopant types between S/D and channel region, are found to effectively solve the formation of the ultra-shallow p-n junction and the increase of thermal budget [2][3][4][5]. Due to its excellent electrical performance, effective suppression of SCEs and compatibility with CMOS process, it is regarded as one of the promising device structures for the continuous scaling in the future [2,[6][7][8][9][10][11][12][13].…”

Subthreshold behavior models for nanoscale junctionless double-gate MOSFETs with dual-material gate stack

“…8) To solve these problems, junctionless (JL) MOSFETs are proposed with a high and uniform impurity concentration within the channel and the source/drain (S/D) regions. [9][10][11][12][13] It has been demonstrated that JL devices have better immunity on SCEs and an ideal subthreshold slope (SS). At present, abundant studies of JL DG MOSFETs and JL surrounding-gate MOSFETs have been performed.…”

Suppression of subthreshold characteristics variation for junctionless multigate transistors using high-k spacers

“…Being worse, this vertical non-uniformity significantly degenerates the subthreshold characteristics of JMTs due to the degraded gate control ability. Further, it becomes a challenge to control the trapezoidal cross section uniform in JMTs due to their narrow Fin body, which induces the variation of subthreshold characteristics [21].…”