Investigation of trench process variation on the recessed-gate junctionless MOSFETs considering the circuit application

Abstract

In this work, we investigate the effect of trench process variation (TPV) on the inverter circuits built by the recessed-gate junctionless MOSFET (JLM). Through numerical simulation, analog parameters of inverters like the propagation delay (t p ) and the static noise margin (SNM) are found to fluctuate seriously due to this random variation. At the same time, subthreshold swing (SS) and threshold voltage of JLMs are found accompanying apparent fluctuations under the TPV and have a strikingly linear relationship with the SNM and t p , respectively. The physics insights of TPV are also analyzed from device level by separating it into the trench shape variation and channel thickness variation, respectively. Then the TPV is found to have a more severe impact on the characteristics of JLMs than the random dopant fluctuation in terms of SS, I on and DIBL. And a processing guideline is offered to ensure a reasonable SS value of the device. Finally, the charge plasma concept is introduced into the N-type recessed-gate JLM for obtaining a superior immunity of the process variation. This work highlights the impact of the TPV and provides a useful guideline to suppress it.