Suppression of subthreshold characteristics variation for junctionless multigate transistors using high-k spacers

Lou, Haijun; Zhang, Baili; Li, Dan; Lin, Xinnan; He, Jin‐Sheng; Chan, Mansun

doi:10.1088/0268-1242/30/1/015008

Cited by 12 publications

(7 citation statements)

References 28 publications

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“…Many researchers are working on the analytical modeling, simulation and fabrication of such technologybased devices. Different studies have been carried out in the literature to obtain better results by applying various ideas on the device structures such as high K dielectric materials [20][21][22], different semiconductor materials [23][24][25][26], high K spacers [27][28][29], mobility enhancement using strain technology [30][31][32][33]. Moreover, multi-gate junctionless transistors to improve gate control have also been studied [12,27,[34][35][36][37][38][39][40][41].…”

Section: Image Sensorsmentioning

confidence: 99%

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

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The Short Channel Effects (SCE) are becoming more prominent in Complementary Metal Oxide Semiconductor (CMOS) circuits with an introduction of nanoscale Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The short channel effects (SCE’s) and fabrication challenges have provoked the researchers to think for some other technologies to enhance the market of semiconductor devices. To overcome these SCE’s, various methodologies such as multi-gate structures, material engineering, gate engineering, dielectric pockets, strain technology, high K dielectric material, heterostructures, source and drain extensions etc. have been implemented. However, at very short channel lengths, the sharp edges of doping are difficult to obtain and thus SCE’s have become so difficult to control even after the implementations of different methodologies. Therefore, a new type of technology has been introduced to overcome such pitfalls e.g. transistors without junctions. Junctionless field effect transistor (JLFET) is one of the technologies which has overcome various SCE’s. Although the research on various issues has been addressed by different authors but still there is an impediment in the commercialization of the same device. The different technology boosters have been incorporated into junctionless based devices to escalate the performance. The technology boosting aspect of junctionless FET has been reviewed in this paper which has not been considered yet. In this paper distinct technology boosters and numerous effects on junctionless devices have been studied and presented. The performance of the junctionless FET devices are studied on incorporating the different semiconductor materials, effect of strain, use of high k dielectric, use of dielectric pockets, effect of gate misalignment, use of heterostructures, silicon on nothing (SON), vertically stacked nanowires, newly proposed rectangular core-shell based junctionless FET’s and roles of various physical parameters such as temperature, nanowire widths and effect of scattering mechanism on the performance of JLFET have been addressed.

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Section: Image Sensorsmentioning

confidence: 99%

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

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“…The primary requirement of Junctionless architecture is high uniform doping concentration from source to drain of (10 19 -10 20 cm -3 ) to sustain high current during ON state and total depletion of the channel during OFF state conditions. The concept of high-k spacers has been presented to improve the device's scalability and operation [10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Electrical Characteristics of 14nm SOI-based Trigate Gaussian Channel Junctionless FinFET

Ramakrishnan,

Alias,

Hamzah

et al. 2023

J. Phys.: Conf. Ser.

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Planar MOSFETs are reaching their physical limits. To overcome the limitations and improve channel gate control, FinFET technology, which uses many gate devices, is a superior choice while lowering the size of planar MOSFETs even further. In this paper, 14nm Silicon-On-Insulator-based Trigate Gaussian Channel Junctionless FinFET is presented. The gate length of 14nm is considered along with an Equivalent Oxide Thickness of 1nm, 5nm as fin width, and the work function of the gate metal is 4.75eV. The device architecture has a non-uniform doping profile (Gaussian distribution) across the fin’s thickness. It is devised to address the effects of Random Dopant Fluctuations such as channel mobility degradation in Junctionless FinFET based devices. The impact of fin height (Fh), gate dielectric and spacer dielectric on the Drain Induced Barrier Lowering, Subthreshold Swing, drain current of GC-JLFinFET is analyzed. The results show that the Ion=101.5μA/μm and Ion/Ioff is 3.2×107 are obtained for the proposed device structure compared to the existing structure, which has Ion/Ioff of 1.1x107. Furthermore, the proposed design shows better efficiency in short channel characteristics, namely DIBL=25.3 mV/V, Subthreshold Swing=63.88 mV/dec and Transconductance =3.621×105 S/μm. Thus the Gaussian Channel-based FinFET architecture can provide optimum results for Junctionless-based FinFET devices.

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“…are usually used as gate insulators and sidewall spacer layers in nanoscale metal-oxidesemiconductor FETs (MOSFETs) because of their high dielectric constant, considerable amount of conduction and valence band offsets with silicon (Si), apart from their thermodynamic stability with Si [11,12]. There have been numerous published works regarding effects of spacer layers on the analogue/RF and digital circuit performance of inversion-mode (IM) [13][14][15] as well as JCTs [16][17][18][19]. Extensive investigations are reported concerning the impact of dual-k spacers on multiple application domains such as analogue, logic and memory circuit performances of IM FinFETs [20][21][22][23] including a recently coined new device architecture, e.g.…”

Section: Introductionmentioning

confidence: 99%

“…a reconfigurable FET [24]. The influences of underlap spacer layers in improving low‐power logic applications for double‐gate JLTs, and also for FinFETs were reported in [18, 19, 25]. Additionally, the enhanced analogue performance of double‐gate JCTs using spacer engineering was investigated in [26, 27].…”

Section: Introductionmentioning

confidence: 99%

Effects of asymmetric underlap spacers on nanoscale junctionless transistors and design of optimised CMOS amplifiers

Roy

Biswas

2019

IET Circuits, Devices & Systems

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Using well-calibrated device simulation, the analogue performance of 20 nm double-gate junctionless transistors (JLTs) is investigated in terms of transconductance (g m), output conductance (g d) for various underlap spacer asymmetricity and dielectric constant (k) values. The spacer length is varied ranging 1-6 nm on both source (L S) and drain sides (L D) while keeping their sum fixed at 12 nm. Obtained results show that for both n-and p-metal-oxide-semiconductor field-effect transistors (FETs), a longer LD increases gm exhibiting weak sensitivity to variations in k while gd increases and decreases with higher and lower k. The present findings reveal that the highest voltage gain of 46.3 and largest gain bandwidth (GBW) of 676 GHz are obtained for complementary metal-oxide-semiconductor (CMOS) amplifiers featuring both n and p transistors with L S = 11 nm, L D = 1 nm and k = 80 and L S = 1 nm, L D = 11 nm and k = 3.9; both figures are quite higher compared with their symmetric counterpart. The studies manifest that such an asymmetric dielectric spacer engineering could be employed in designing high performance nanoscale CMOS amplifiers without increasing hardly any process complexity and cost while providing augmented GBW compared with reported amplifiers based on molybdenum disulphide transistors and tunnel FETs.

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Suppression of subthreshold characteristics variation for junctionless multigate transistors using high-k spacers

Cited by 12 publications

References 28 publications

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Design and Analysis of Electrical Characteristics of 14nm SOI-based Trigate Gaussian Channel Junctionless FinFET

Effects of asymmetric underlap spacers on nanoscale junctionless transistors and design of optimised CMOS amplifiers

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