Effects of Electrochemical Etching on InP HEMT Fabrication

Saranovac, Tamara; Ruiz, Diego Calvo; Han, Daxin; Arabhavi, Akshay M.; Ostinelli, O.; Bolognesi, C. R.

doi:10.1109/tsm.2019.2940320

Cited by 6 publications

(5 citation statements)

References 8 publications

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“…For example, an electrode reaction between a substrate and deionized water has been reported [8], as well as the occurrence of electrochemically induced etching nonuniformities, depending on the conductivity of the substrate [9,10]. There are also reports that etching behavior differs depending on the surface material of the ohmic electrode and the size of the monitor opening [5,11]. In the manufacture of compound semiconductor devices, Au is generally used as the uppermost metal electrode layer.…”

Section: Introductionmentioning

confidence: 99%

Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

et al. 2022

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We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13 μm–0.16 μm to suit the intended application. The core processes are a two‐step electron‐beam lithography process using a three‐layer resist and gate recess etching process using citric acid. An electron‐beam lithography process was developed to fabricate a T‐shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three‐layered resist and two‐step electron beam exposure and development. Citric acid‐based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.

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Section: Introductionmentioning

confidence: 99%

Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

et al. 2022

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“…After the gate metal liftoff, Pt is diffused controllably thorough the InP etch stop and part of the AlInAs barrier with nanometer precision. [ 11 ] To determine the impact of the diffusion depth of our sunk gates, an additional sample was processed in parallel using a lower Pt thickness (3 instead of 4 nm) during the gate metal evaporation with the same offset gate configuration as detailed previously. As shown in Figure a, the device with thinner Pt exhibits reduced leakage current due to the increased gate‐to‐channel distance (72% lower leakage at V GS = 0.3 V and V DS = 0.75 V).…”

Section: Discussionmentioning

confidence: 99%

“…In both cases, the T‐gate electrode was formed by evaporation of a Pt/Ti/Pt/Au metal stack in the center of the gate recess region to center gate foot in the recess (symmetric recess but offset gate position) after a two‐step EBL process. The gates were sunk through the InP etch stop and into the AlInAs barrier as per the study given by Saranovac et al [ 11 ] and passivated with a 15 nm Al 2 O 3 layer by atomic layer deposition (ALD). Careful investigation with focused ion beam (FIB) on both structures confirmed a 50 nm gate footprint, as shown in Figure .…”

Section: Process Technologymentioning

confidence: 99%

Impact of Reduced Gate‐to‐Source Spacing on Indium Phosphide High Electron Mobility Transistor Performance

Ruiz

Han

Bonomo

et al. 2020

Physica Status Solidi (a)

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Indium phosphide (InP)‐based high electron mobility transistors (HEMTs) with an offset gate enable higher maximum oscillation frequency (fMAX) values because of the resulting reduction in gate‐to‐source resistance. Following this approach, improved direct current (DC) characteristics and cutoff frequencies (fT/fMAX > 410/710 GHz with LG = 50 nm) are shown with respect to centered gate devices. However, HEMTs with an offset gate show degraded noise performances compared with centered gate devices because of a higher gate leakage current. The results show that offsetting the gate closer to the source is not desirable for ultra‐low‐noise performance.

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“…Subsequently, the sample was rinsed in a fresh DMSO to eliminate any residual metal particles. To protect the delicate 2D layer from the impact of strong solvents, unlike e.g., compound semiconductors [35], For contact lithography, an image reversal process was employed. To execute this, an initial spin-coating of the LOR was performed at 5000 rpm for 30 s, followed by baking at 150 • C for 5 min.…”

Section: Photolithography Of 2d-tmdc Layermentioning

confidence: 99%

“…Subsequently, the sample was rinsed in a fresh DMSO to eliminate any residual metal particles. To protect the delicate 2D layer from the impact of strong solvents, unlike e.g., compound semiconductors [35], it is essential to avoid prolonged exposure or subjecting the sample to high-temperature DMSO treatment. The failed process due to using high temperature DMSO is shown later in this section.…”

Section: Photolithography Of 2d-tmdc Layermentioning

confidence: 99%

Optimization of Layer Transfer and Photolithography for Device Integration of 2D-TMDC

Ghiami,

Sun,

Fiadziushkin

et al. 2023

Crystals

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Extensive research into two-dimensional transition metal dichalcogenides (2D-TMDCs) over the past decade has paved the way for the development of (opto)electronic devices with enhanced performance and novel capabilities. To realize devices based on 2D-TMDC layers, compatible and optimized technologies such as layer transfer and photolithography are required. Challenges arise due to the ultrathin, surface-only nature of 2D layers with weak van der Waals adhesion to their substrate. This might potentially compromise their integrity during transfer and photolithography processes, in which prolonged exposure at usually high temperature to reactive chemicals and strong solvents are conventionally used. In this paper, we show that employing a dry-transfer technique based on thermal release tape (TRT) as an alternative to wet processes based on KOH solution better preserves layer quality. In the succeeding device fabrication process, an optimized photolithography as a cost-effective and widely available method for device patterning is utilized. The introduced photolithography protocol presents a near-perfect yield and reproducibility. To validate our optimized techniques, we fabricated field-effect transistors (FETs) using 2D-MoS2 layers from metal–organic chemical vapor deposition (MOCVD), wet- and dry-transferred onto SiO2/Si substrates. Our findings mark a significant stride towards the efficient and industry-compatible utilization of 2D van der Waals materials in device fabrication.

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Effects of Electrochemical Etching on InP HEMT Fabrication

Cited by 6 publications

References 8 publications

Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

Impact of Reduced Gate‐to‐Source Spacing on Indium Phosphide High Electron Mobility Transistor Performance

Optimization of Layer Transfer and Photolithography for Device Integration of 2D-TMDC

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