Effects of annealing temperature on the characteristics of HfSixOy/HfO2 high-k gate oxides

Abstract

We have investigated the effects of annealing temperature on the physical and electrical properties of the HfSixOy/HfO2 thin film for high-k gate oxides in a metal-oxide-semiconductor device. The oxidation and subsequent postoxidation N2 annealing at 500 °C of Hf deposited directly on the Si substrate results in the HfSixOy/HfO2 stack layer with excellent electrical properties. For instance, we observe a negligible hysteresis window, an excellent equivalent oxide thickness (1.2 nm), and a low leakage current density (⩽4×10−5 A/cm2 at 2 V after compensating the flatband voltage shift). However, the formation of an interfacial SiOx layer enhances as annealing temperature increases. Based on current observation, we suggest that annealing temperature must be carefully controlled to obtain the excellent electrical properties of HfO2/HfSixOy high-k gate oxides.

A double-layer current conduction model for high-κ gate dielectric materials with interfacial oxide or silicate layer

“…The very good fitting in the high voltage regime (see the continuous curve in Fig. 3) confirms the double-layer structure of the asdeposited HfO 2 on a silicon substrate [10,15,16]. It is noted that as hafnium oxide is only marginal stable with Si substrate [28], a thin layer chemical silicon oxide was introduced on purpose to suppress the formation of hafnium silicide during atomic layer deposition (ALD).…”

“…Some structural and electronic parameters are allowed for adjustment, in a fitting procedure on the experimental data. Due to the very accurate fitting results, we were able to confirm the double-layer structure of the thermally grown HfO 2 on a silicon substrate [10,15,16]. The interlayer was identified as SiO 2 , in accordance with other independent results [15] and estimates of its width have been obtained for each sample.…”

“…Thus, it was observed that the I-V diagrams reveal quite sharp slope breaking points [11,13], with relative steep increase of the current, suggesting that a direct tunneling mechanism is switched on beyond some voltage range. As the total dielectric thickness may be larger than 10 nm, it follows that such a peculiar behavior can be only explained by a heterogeneous composition of the gate dielectric [10,15,16]. We report in this paper an I-V analysis performed on MOS capacitors obtained by oxidation of the as-deposited Hf oxides.…”

“…Nevertheless, new difficulties are brought in: physically thicker high-j gate dielectric films give rise to several reliability problems and deteriorate the performances of the MOS devices. Therefore, understanding the structural properties and the physics of the electron transport through such ultra-thin high-j gate dielectrics became a new battlefield for MOS electronics in recent years [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20].…”

Electrical properties of ultrathin HfO2 gate dielectrics on partially strain compensated SiGeC/Si heterostructures

“…5, the change of EOT is much less for N 2 annealing though the leakage current density is found to be lower in O 2 annealed samples. This is due to the increase of interfacial layer thickness during O 2 annealing [30,31] which, consequently, leads to the reduction of the leakage current density. Figure 6 shows the hysteresis width in C-V characteristics and interface trap densities at the HfO 2 /Si 0.69 Ge 0.3 C 0.01 interface as a function of annealing temperature in O 2 and N 2 ambients.…”