2004
DOI: 10.1116/1.1743119
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Effects of annealing temperature on the characteristics of HfSixOy/HfO2 high-k gate oxides

Abstract: We have investigated the effects of annealing temperature on the physical and electrical properties of the HfSixOy/HfO2 thin film for high-k gate oxides in a metal-oxide-semiconductor device. The oxidation and subsequent postoxidation N2 annealing at 500 °C of Hf deposited directly on the Si substrate results in the HfSixOy/HfO2 stack layer with excellent electrical properties. For instance, we observe a negligible hysteresis window, an excellent equivalent oxide thickness (1.2 nm), and a low leakage current d… Show more

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Cited by 13 publications
(10 citation statements)
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“…The very good fitting in the high voltage regime (see the continuous curve in Fig. 3) confirms the double-layer structure of the asdeposited HfO 2 on a silicon substrate [10,15,16]. It is noted that as hafnium oxide is only marginal stable with Si substrate [28], a thin layer chemical silicon oxide was introduced on purpose to suppress the formation of hafnium silicide during atomic layer deposition (ALD).…”
Section: Resultssupporting
confidence: 58%
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“…The very good fitting in the high voltage regime (see the continuous curve in Fig. 3) confirms the double-layer structure of the asdeposited HfO 2 on a silicon substrate [10,15,16]. It is noted that as hafnium oxide is only marginal stable with Si substrate [28], a thin layer chemical silicon oxide was introduced on purpose to suppress the formation of hafnium silicide during atomic layer deposition (ALD).…”
Section: Resultssupporting
confidence: 58%
“…Some structural and electronic parameters are allowed for adjustment, in a fitting procedure on the experimental data. Due to the very accurate fitting results, we were able to confirm the double-layer structure of the thermally grown HfO 2 on a silicon substrate [10,15,16]. The interlayer was identified as SiO 2 , in accordance with other independent results [15] and estimates of its width have been obtained for each sample.…”
Section: Introductionmentioning
confidence: 65%
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“…5, the change of EOT is much less for N 2 annealing though the leakage current density is found to be lower in O 2 annealed samples. This is due to the increase of interfacial layer thickness during O 2 annealing [30,31] which, consequently, leads to the reduction of the leakage current density. Figure 6 shows the hysteresis width in C-V characteristics and interface trap densities at the HfO 2 /Si 0.69 Ge 0.3 C 0.01 interface as a function of annealing temperature in O 2 and N 2 ambients.…”
Section: Resultsmentioning
confidence: 96%