Effectiveness of Thin‐film Barrier Metals for Eutectic Solder Bumps

Honma, S.; Tateyama, K.; Yamada, Hiroshi; Doi, K.; Hirano, N.; Okada, Toshiki; Aoki, Hideo; Hiruta, Y.; Sudô, Toshio

doi:10.1108/13565369710368151

Cited by 3 publications

(2 citation statements)

References 4 publications

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“…Our investigation concluded that the thin f i structure has a good thermal stability at the interface of solder bumps and A1 pads [6] [7]. Therefore, we choose this structure for the barrier metal.…”

Section: Discussionmentioning

confidence: 95%

Eutectic solder bumped flip chip development

Akashi

Chikai

Hamano

et al.

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium

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Recently, smaller, thinner and higher density packaging technology is demanded. Flip chip interconnection is one of solution to these demands. We developed solder bumping and wafer sorting process for bear dice with eutectic solder bumps. The highlights of our solder bumping and wafer sorting process and the reliability test results will be shown. The results proved that our bare chips have good reliability, allowing the bumping process to be applied to mass production product. Next we will report some experimental results of wafer sorting process. Wafer sorting process is the key process for mass production of bare chips. For peripherally bumped bare chips, we chose a conventional type of probing card, the cantilever needle card. We made some experiments with four cards which had different needle heads, and decided the best head shape. Using the best card, we investigated the relationship between the overdrive and the amount of bump height deformation. We demonstrated that the deformation can be controlled smaller than 5pm when operating 75pm overdrive from all pin contact. The card can be cleaned better by brushing than by polishing to ceramic plates. To choose probing cards for area bumped bare chips, we made some experiments with three types of probing cards: the cantilever type, the bumped type, and,the cobra type. Results showed the cobra type is best suited to area bumps. IntroductionHigh pin count, high speed response and high density packaging are the key points of recent semiconductor packaging tedmology. There are three types of technologies for interconnection which are now already available, wire-bonding (WB), tape automated bonding (TAB), and flip chip

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Section: Discussionmentioning

confidence: 95%

Eutectic solder bumped flip chip development

Akashi

Chikai

Hamano

et al.

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium

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“…Eutectic solder flip chip has some advantages such as good bonding yield by good wettability and applicability to low cost substrate like warped substrate or typical organic substrate which can not endure high temperature. Eutectic solder flip chip interconnection technology has been developed in Toshiba and some reliability and packaging issue were reported [5], [6]. Estimation of capillary action in underfilling process has also been in progress [7].…”

Section: Introductionmentioning

confidence: 99%

Eutectic solder flip chip technology-bumping and assembly process development for CSP/BGA

Aoki

Takubo²,

Nakazawa³

et al.

1997 Proceedings 47th Electronic Components and Technology Conference

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Eutectic solder flip chip fabrication technology, through bumping to assembly process, has been developed. In bumping process, electroplating method and thick photo resist process could form eutectic solder bumps whose uniformity of height are less than 10 % within wafer. Eutectic solder flip chip assembly process, which includes bonding, cleaning and underfilling, has been also developed. Bonding process of eutectic solder indicates good self-alignment. The excellent rosin cleaning was achieved by the ultrasonic cleaning process with Techno Care @. In underfilling process, the underfill resin which can be applied to small stand-off have been chosen. Reliability tests for CSP and flip chip interconnection were carried out and confirmed the good reliability of fabrication process using eutectic solder flip chip technology.

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Eutectic solder bump process for ULSI flip chip technology

Ezawa

Miyata²,

Inoue³

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium

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A novel eutectic solder bump process, which allows ULSI chips area array pad layout, has been developed. Straight side wall bumps as plated using a new nega-type photo resist and eutectic solder electroplating provide several advantages over conventional mushroom bumps. The novel developed process gives the bump height uniformity as reflowed of less than 10 % within wafer.Composition measurements using ICP spectrometry have been performed to investigate the bump height dependence on solder compositions and the metal content dependence of a plating solution on the

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Effectiveness of Thin‐film Barrier Metals for Eutectic Solder Bumps

Cited by 3 publications

References 4 publications

Eutectic solder bumped flip chip development

Eutectic solder bumped flip chip development

Eutectic solder flip chip technology-bumping and assembly process development for CSP/BGA

Eutectic solder bump process for ULSI flip chip technology

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