Eutectic solder flip chip technology-bumping and assembly process development for CSP/BGA

Aoki, Hideo; Takubo, C.; Nakazawa, T.; Honma, S.; Doi, K.; Miyata, Masahiro; Ezawa, Hirokazu; Hiruta, Y.

doi:10.1109/ectc.1997.606188

Cited by 11 publications

(3 citation statements)

References 8 publications

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“…The resulting completed flip chip assembly is much smaller than a traditional carrier-based system; the chip sits directly on the circuit board, and is much smaller than the carrier both in area and height. The short wires greatly reduce inductance, allowing higher-speed signals, and also conduct heat better [1][2].…”

Section: Introductionmentioning

confidence: 99%

Flip Chip Underfill for High Density Semiconductor Packaging

Qin¹,

Tao²,

Han³

et al. 2014

ECS Trans.

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The trends of flip chip technology are lead free, reduced bump pitch design, low-k wafer, large die, etc. These technologies bring challenges to flip chip underfill. Lead free solder bumps also have less solder fatigue resistance compared to traditional solder. Low-k materials are mechanically weak and fragile which request underfill have higher modulus and Tg to lower stress on solder bump, and lower modulus and Tg to lower stress on Si die. Flip chip underfill need balances properties, such as Tg, modulus, and CTE. This study did research on hardener, filler and rubber. The new amine chemistry allows for leap in performance in large die, lead-free and low-k applications. The Features of the underfill are Low stress, tailored Tg and modulus, low CTE, High fracture resistance and large processing window.

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Section: Introductionmentioning

confidence: 99%

Flip Chip Underfill for High Density Semiconductor Packaging

Qin¹,

Tao²,

Han³

et al. 2014

ECS Trans.

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“…Sn-Ag solder bump heights were measured by a focus point detection method. For higher reliable CSP packages, bump heights of more than 70 pm as reflowed are necessary [3,4]. The present bump process can easily provide the required bump heights.…”

Section: Figure 2 Cross-sectional Sem View Of the Plating Maskmentioning

confidence: 97%

“…We previously reported that the novel eutectic Sn-Pb alloy electroplated bump process is well qualified to have high reliable flip chip interconnection for CSPs and BGAs [4,5,6]. The current environmentally conscious manufacturing moves towards Pb-free schemes for electronic devices and components.…”

Section: Introductionmentioning

confidence: 99%

Eutectic Sn-Ag solder bump process for ULSI flip chip technology

Ezawa¹,

Miyata²,

Honma³

et al.

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)

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The novel developed Sn-Ag eutectic solder bump process provides several advantages over conventional solder bump process schemes. Steep wall bumps as plated were fabricated using the nega-type photo resist with a thickness of more than 50pm by one time spin coating. This improves productivity for mass production. The 2-step electroplating process was performed using separate plating reactors for Ag and Sn. The eutectic Sn-Ag alloy bumps were easily obtained by annealing the metal stacks with Sn layer on Ag layer sequentially electroplated. This electroplating process does not need to strict control of the content ratio of Ag to Sn in an alloy plating solution even with increasing electroplating depositions. The novel developed process gives the withinwafer uniformity of the bump height as reflowed of less than 10 % and of the Sn-Ag alloy composition as reflowed of less than ~S w t . ' %~A g , analyzed by ICP spectrometry. Shear strength measurements were performed to know thermal stability for the structure of Cu padsiTi/Ni/Pd/Sn-Ag eutectic solder stack. In the case of the Ti (100nm)/Ni (300nm)Pd (50nm) barrier metal stacks, the shear strength after 5 times annealing in N2 ambience at 260°C decreased to 70% than that as reflowed. As the Ti becomes thicker in the Ti/Ni/'Pd metal stack, shear strengths are improved. Comparing the structure of Cu/Ti/NiPd/Sn-Ag eutectic solder with the case of Ta/Ti/Ni/Pd and Nb/Ti/Ni/Pd barrier metal stacks, the analysis results of Auger spectrometry show that Sn drfision into Cu to form Cu-Sn alloy was observed only in Cu/Ta/Ti/Ni/Pd barrier metal stacks. These results suggest that the same Ti/Ni/Pd barrier metal stack as used in Sn-Pb solder bump and Au bump is viable for ULSIs with Cu interconnects.

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