Recently, smaller, thinner and higher density packaging technology is demanded. Flip chip interconnection is one of solution to these demands. We developed solder bumping and wafer sorting process for bear dice with eutectic solder bumps. The highlights of our solder bumping and wafer sorting process and the reliability test results will be shown. The results proved that our bare chips have good reliability, allowing the bumping process to be applied to mass production product. Next we will report some experimental results of wafer sorting process. Wafer sorting process is the key process for mass production of bare chips. For peripherally bumped bare chips, we chose a conventional type of probing card, the cantilever needle card. We made some experiments with four cards which had different needle heads, and decided the best head shape. Using the best card, we investigated the relationship between the overdrive and the amount of bump height deformation. We demonstrated that the deformation can be controlled smaller than 5pm when operating 75pm overdrive from all pin contact. The card can be cleaned better by brushing than by polishing to ceramic plates. To choose probing cards for area bumped bare chips, we made some experiments with three types of probing cards: the cantilever type, the bumped type, and,the cobra type. Results showed the cobra type is best suited to area bumps. IntroductionHigh pin count, high speed response and high density packaging are the key points of recent semiconductor packaging tedmology. There are three types of technologies for interconnection which are now already available, wire-bonding (WB), tape automated bonding (TAB), and flip chip
Recently, Power devices have gotten a lot of attention in order to achieve low power consumption and downsizing for electrical equipment. Under such conditions, power packages are strongly required to have high heat dissipation structure with low on-state resistance and low inductance to decrease low power loss and high-speed switching noise. Panel Level Package (PLP TM) gives advantages on productivity, reliability and high-speed transmission characteristics. In this paper, we observed temperature rise at a line and vias during applying current of over 100 A to understand their design in PLP TM. We also simulated temperature distribution of the same model to research thermal behavior and compared with observed result.
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