Effective Vectorization with OpenMP 4.5

Abstract

This paper describes how the Single Instruction Multiple Data (SIMD) model and its extensions in OpenMP work, and how these are implemented in different compilers. Modern processors are highly parallel computational machines which often include multiple processors capable of executing several instructions in parallel. Understanding SIMD and executing instructions in parallel allows the processor to achieve higher performance without increasing the power required to run it. SIMD instructions can significantly reduce the runtime of code by executing a single operation on large groups of data. The SIMD model is so integral to the processor's potential performance that, if SIMD is not utilized, less than half of the processor is ever actually used. Unfortunately, using SIMD instructions is a challenge in higher level languages because most programming languages do not have a way to describe them. Most compilers are capable of vectorizing code by using the SIMD instructions, but there are many code features important for SIMD vectorization that the compiler cannot determine at compile time. OpenMP attempts to solve this by extending the C++/C and Fortran programming languages with compiler directives that express SIMD parallelism. OpenMP is used to pass hints to the compiler about the code to be executed in SIMD. This is a key resource for making optimized code, but it does not change whether or not the code can use SIMD operations. However, in many cases critical functions are limited by a poor understanding of how SIMD instructions are actually implemented, as SIMD can be implemented through vector instructions or simultaneous multi-threading (SMT). * We have found that it is often the case that code cannot be vectorized, or is vectorized poorly, because the programmer does not have sufficient knowledge of how SIMD instructions work. * In this TR we will not cover how OpenMP SIMD is implemented using SMT on GPUs. Implementations using this approach are a work in progress * Long doubles cannot be vectorized.

Compiler-Assisted Compaction/Restoration of SIMD Instructions

“…However, in a vector architecture, conditional statements do not have a binary nature, since each element of the vector register can provide a different result to the conditional test. This is known as the divergence control problem, and appears frequently in vectorized codes [17]. Previous studies indicate that at least 10% of the most common vectorizable loops have divergence control issues [22].…”

“…Vectorized applications offer better performance, higher energy efficiency and greater resource utilization [16]. However, the code vectorization process has several obstacles to overcome, such as horizontal operations 1 , data structure conversion, or divergence control, the most challenging being the latter one [17]. Ultimately, the effectiveness of a vector architecture depends on its ability to vectorize large quantities of code [18].…”

A Case Study of LLVM-Based Analysis for Optimizing SIMD Code Generation

“…However, it is not uncommon for a transformation to be correct but unable to be statically verified by the compiler. Since OpenMP 4.0, OpenMP has added support for the SIMD directive, which provides a cross-platform method for statically asserting information about the program's semantics to the compiler's vectorization pass [7]. In DCA++, various loops require additional information to be successfully vectorized.…”

Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions

“…The divergence control problem appears frequently when executing vectorized codes [19]. Previous studies indicate that at least 10% of the most common vectorizable loops have divergence control issues [8].…”

“…Ultimately, the effectiveness of a vector architecture depends on its ability to vectorize large quantities of code [34]. However, the code vectorization process incurs in several obstacles to overcome, such as horizontal operations, data structure conversion or divergence control, the most challenging being the latter one [19]. While there are many ways to implement divergence control [35], predicated execution is the most common in current vector architectures.…”