Effective Thermal Via and Decoupling Capacitor Insertion For 3D System-On-Package

Wong, Eric; Minz, J.R.; Lim, Sung Kyu

doi:10.1109/ectc.2006.1645903

Cited by 11 publications

(4 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As with many other new technologies, TSVs still face many critical issues. In the development of TSVs, the following must be noted and understood (Lau, 2009a(Lau, , b, c, 2010a(Lau, , b, 2011Lau et al, 2010a, b;Lau and Tang, 2009;Yu et al, 2008aYu et al, , b, 2009aTang et al, 2010;Chen et al, 2008c;Premachandran et al, 2008;Zhang et al, 2009a, b;Hoe et al, 2009;Choi et al, 2009;Vempati et al, 2009;Khan et al, 2008Khan et al, , 2009Sekhar et al, 2008;Ho et al, 2008;Selvanayagam et al, 2009;Sekiguchi et al, 2006;Takahashi and Sekiguchi, 2006;Garrou et al, 2009;Ramm et al, 2008;Andry et al, 2008;Knickerbocker et al, 2008;Kumagai et al, 2008;Sunohara et al, 2008;Lee et al, 2007;Matsuo et al, 2000;Wong et al, 2006;Beica et al, 2008;Wolf et al, 2008;Henry et al, 2008):…”

Section: Critical Issues Of Tsvmentioning

confidence: 99%

Overview and outlook of through‐silicon via (TSV) and 3D integrations

Lau

2011

Microelectronics International

278

View full text Add to dashboard Cite

Purpose -The purpose of this paper is to focus on through-silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented. Design/methodology/approach -This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for highpower, high-performance, high pin-count, ultra fine-pitch, small real-estate, and low-cost applications. To achieve this, the design uses chip-to-chip interconnections through a passive TSV interposer in a 3D IC integration system-in-package (SiP) format with excellent thermal management. Findings -A generic, low-cost and thermal-enhanced 3D IC integration SiP with a passive interposer has been proposed for high-performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high-power chips on top and low-power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to "dig" holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (.99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin-wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high-power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper-filled TSV interposer and the high-and low-power chips are recommended to reduce creep damage of the lead-free microbump solder joints and prolong their lives. Originality/value -The paper's findings will be very useful to the electronic industry.

show abstract

Section: Critical Issues Of Tsvmentioning

confidence: 99%

Overview and outlook of through‐silicon via (TSV) and 3D integrations

Lau

2011

Microelectronics International

278

View full text Add to dashboard Cite

show abstract

“…To address these needs, silicon interposers with TSV have emerged as a good solution to provide high wiring density interconnection, while minimizing CTE mismatch to the silicon chip that is vulnerable to thermal-mechanical stress, and improving electrical performance due to shorter interconnection from chip to substrate [3,4]. However, the introduced TSV interposer affects thermal path of the package and hence affects the package thermal performance [5,6,7].…”

Section: Introductionmentioning

confidence: 99%

“…Assuming the effective thermal conductivity of the BU substrate is 1.5 W/m/°C , and using the geometry shown in the figure. According to Robert[7], R − refer to the thermal spreading resistance from the heat source to interposer and thermal spreading resistance from the interposer to substrate, respectively.…”

mentioning

confidence: 99%

Effect of TSV interposer on the thermal performance of FCBGA package

Hoe

Yue²,

Pinjala

et al. 2009

2009 11th Electronics Packaging Technology Conference

View full text Add to dashboard Cite

In this paper, the effect of TSV (Through Silicon Via) parameters on the equivalent thermal conductivity of TSV interposer and the effect of the TSV interposer on the thermal performance of the package have been elaborated. The modeling approach using in this paper includes compact modeling for the package and detailed modeling for the TSV interposer. The objective of compact modeling is to study the effect of TSV interposer on thermal performance of the package, while the objective of detailed modeling is to extract the equivalent thermal conductivity of TSV interposer which is used for compact modeling. The proposed package in this study includes a large die with fine pitch, a silicon interposer with TSV, a 1-2-1 buildup substrate and a PCB board. In addition, to evaluate the thermal performance of the proposed package, a similar package without the TSV interposer is also modeled in this study for comparison. The results of detailed modeling show that the equivalent thermal conductivity of TSV interposer can be increased by reducing the pitch and via ratio of TSV, as well as increasing the plating thickness of partial filled TSV and using highly conductive filler material. Furthermore, the results of compact modeling reveal that the proposed TSV interposer improves the thermal performance of the package. The thermal resistance of the package decreases when the interposer size and thickness increase, and the equivalent thermal conductivity of TSV interposer has negligible effect on thermal performance of the package.

show abstract

“…In these works, the resistive and inductive effects of a 3D P/G grid were used to calculate the decap budget for each placed module. Considering decaps during placement reduced the total number of decaps needed to adequately reduce the power supply noise [16]. In addition to using decaps to reduce P/G noise, the density of P/G TSVs can be adjusted to reduce the power supply noise [17].…”

Section: B Related Workmentioning

confidence: 99%

Three-dimensional integrated circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis

Falkenstern

Xie

Chang

et al. 2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

View full text Add to dashboard Cite

Abstract-Three Dimensional Integrated Circuits (3D ICs) are currently being developed to improve existing 2D designs by providing smaller chip areas and higher performance and lower power consumption. However, before 3D ICs become a viable technology, the 3D design space needs to be fully explored and 3D EDA tools need to be developed. To help explore the 3D design space and help fill the need for 3D EDA tools, the 3D Floorplan and Power/Ground (P/G) Co-synthesis tool is developed in this work, which develops the floorplan and the P/G network concurrently. Most current 3D IC floorplanners neglect the effects of the 3D P/G network on the design, which may lead to large IR drops in the circuit. To create feasible floorplans with efficient P/G networks, the 3D Floorplan and P/G Co-synthesis tool optimizes the floorplan in terms of wirelength, area and P/G routing area and IR drops. The tool integrates a 3D B*-tree floorplan representation, a resistive P/G mesh, and a Simulated Annealing (SA) engine to explore the 3D floorplan and P/G network. The results of experiments using the 3D Floorplan and P/G Co-synthesis tool show that 3D ICs tend to increase the P/G routing area while decreasing the IR drops in the circuit. By considering the IR drop while floorplanning, exploring the 3D P/G design space, and evaluating 3D IC's effect on 3D P/G networks, the 3D Floorplan and P/G Co-synthesis tool can develop a more efficient 3D IC.

show abstract

Effective Thermal Via and Decoupling Capacitor Insertion For 3D System-On-Package

Cited by 11 publications

References 12 publications

Overview and outlook of through‐silicon via (TSV) and 3D integrations

Overview and outlook of through‐silicon via (TSV) and 3D integrations

Effect of TSV interposer on the thermal performance of FCBGA package

Three-dimensional integrated circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis

Contact Info

Product

Resources

About