Effective design and implementation of GSS‐PLL under voltage dip and phase interruption

Abstract

The robust operation of grid-connected converters under non-ideal grids is a challenging topic. Synchronising of converters requires accurate estimation of the grid vector angle which is traditionally performed by phase locked loops (PLLs). Separating the grid voltage and current sequence components is essential for controlling converters under non-ideal grids. In this study, an efficient method to separate the grid sequence components using cascaded delayed signal cancellation (CDSC) is developed. The proposed method is a reduced version of the conventional delayed signal cancellation separation technique. Implementing CDSC in the stationary frame enables for using a higher bandwidth without degrading its filtering capability which enables for using the GSS as a pre-filter stage for the traditional synchronous reference frame PLL. Therefore, the obtained grid sequence separator PLL (GSS-PLL) accurately estimates the grid vector angle under severe conditions. The performance of GSS method as well as GSS-PLL is compared to the conventional multiple second-order generalised integrator (MSOGI) method under unbalance, phase interruption and harmonically distorted grids. The accuracy of the proposed method is verified through simulation and experimental tests. The low computational effort of GSS scheme compared to the MSOGI is a significant advantage which encourages its implantation for most of the grid-connected converters.

Virtual Park‐based control strategy for grid‐connected inverter interfaced renewable energy sources

“…The derivation of active and reactive power with the FCPs in (20) and (21) can be written by using (18) and (19) as follows [33,34]:…”

“…The reference currents in the STRF plane are computed based on the references powers and the PNS voltage components and the FCPs. The reference current signals I αref , I βref without the CLC are expressed by inserting (36) and (37) into (18) and (19). The total reference currents without the CLC are written in (39).…”

“…In this case, a fast and robust sequence extraction is required in the synchronous reference frame (SRF) [10] or stationary reference frame (STRF) [11]. The complexcoefficient filter-based techniques such as multiple complex coefficient filter (MCCF) [12][13][14], dual second-order generalised integrator (DSOGI)-based techniques [15,16], recursive least squares-based sequence extraction [17], the delay signal cancellation (DSC) sequence extractors [18,19], multiple reducedorder generalised integrator [20], third-order sinusoidal signal integrator (TOSSI) [5] are used to separate symmetrical components. However, the structures of these methods are more complex and have slower sag detection (more than once cycle-20 ms).…”

PLL with frequency and initial‐phase‐angle detectors: performance analysis and speed/robustness trade‐off improvement

“…Recent techniques for development of high-performance PLLs have been based on a moving average filter (MAF) [6][7][8][9][10][11][12], delayed signal cancellation (DSC) [13][14][15][16][17][18][19], complex-coefficient/complexvector filter [20,21], Fourier transform [22], transfer delay [18,23,24] and multiple synchronous reference frame (MSRF)/decoupling network (DN) [25,26]. The MAF-based PLLs continue to be developed because they have a simple structure, low computational burden, good stability and high filtering capability [1,12,27].…”

Power and Voltage Control for Single-Phase Cascaded H-Bridge Multilevel Converters under Unbalanced Loads

“…The grid voltage phase angle is essential in the coordinate transformation; therefore, a phase-locked loop (PLL) is employed to synchronize the output voltage with the grid voltage vector [18]. To accurately obtain the information on the grid voltage including the amplitude and phase angle, some advanced PLLs have been proposed, such as hybrid filtering technique-based PLL [19], grid sequence separator PLL [20], frequency-fixed SOGI-based PLL [21], and repetitive learning-based PLL [22]. However, the computational complexity of coordinate transformation and PLL increases the calculation burden of the embedded processor like the digital signal processor (DSP) [23].…”