PLL with frequency and initial‐phase‐angle detectors: performance analysis and speed/robustness trade‐off improvement

Zarei, Mohammad Mahdi; Karimadini, Mohammad

doi:10.1049/iet-pel.2018.6001

Cited by 7 publications

(10 citation statements)

References 31 publications

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“…This approach is now customary in works directed at improving the PLLs' dynamic performance, taking the harmonics elimination for granted by using adaptive MAFs. For instance, Zarei and Karimadini [25] propose adding "initial phase-angle detectors" and adaptive MAFs, pursuing dynamic enhancements. Similarly, Vukadinović, et al [26] propose a PLL based on Hedge-Algebra-involving Fuzzy Logic-for which its tuning parameters are adjusted through an evolutionary algorithm, depending on the expected disturbance.…”

Section: Discussionmentioning

confidence: 99%

“…Its dynamic behavior, subject of further research in this line, can be enhanced as that of proposals based on the adaptive MAF. For instance, the HB can be taken outside of the loop, as for the EPMAF-PLL, explored in [24], or the topologies in [10,25]. Likewise, the approach taken by Xie, et al [27] would enable preserving the current HB-PLL structure, i.e., having the HB in-loop.…”

Section: Discussionmentioning

confidence: 99%

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A Non-Adaptive Single-Phase PLL Based on Discrete Half-Band Filtering to Suppress Severe Frequency Disturbances

2020

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The interconnection of new generating and storing devices to the power grid imposes the necessity of synchronizing, so the power flow can be manipulated and distributed. In the presence of an increasingly perturbed electric grid, many proposals of novel and modified synchronization techniques attained enough robustness to deal with known perturbations. However, such proposals exhibit drawbacks on their own, leaving open enhancement opportunities, mostly over their discrete implementation—e.g., sampling issues and not-considered inter/harmonics—and their inherent complexity—e.g., the need for frequency adaptability. In this work, three traditional synchronous reference frame (SRF) phase-locked loops (PLL) are modified to implement discrete filtering, such as the well-known proposals based on moving average filters (MAFs), to avoid the problems mentioned above, known for affecting the MAF’s performance. This proposal makes use of discrete, efficient units modularly assembled to yield a signal’s average, based on elliptic half-band filters. The proposed PLLs were tested and exhibited clear advantages—robustness against frequency disturbances—over MAF-based equivalents at standardized tests over a typical simulation environment, setting through this work an initial milestone for its verification and further incorporation in more complex synchronization topologies.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

A Non-Adaptive Single-Phase PLL Based on Discrete Half-Band Filtering to Suppress Severe Frequency Disturbances

2020

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“…Obtaining the grid synchronization signal such as the frequency, phase and amplitude of the grid voltage is the premise and basis for the grid connection operation. The phase-locked loop (PLL) technology can effectively detect the grid synchronization signal in real time and has been widely used [4]. However, due to the large number of power electronic loads such as uncontrolled rectification and reactive power compensation, the power grid is unbalanced or harmonically distorted [5], [6].…”

Section: Introductionmentioning

confidence: 99%

Design of a High Performance Phase-Locked Loop With DC Offset Rejection Capability Under Adverse Grid Condition

2020

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In the new energy grid-connected power generation system, accurately extracting the grid synchronization signals such as the frequency, phase and amplitude of the grid voltage is the basis for effective control. Aiming at the requirements for detecting grid synchronization signals under unbalanced, harmonics and DC offset voltage mixed conditions, a dual second-order complex coefficient filter with DC offset rejection capability (DSOCCF dc) is proposed, combining the approach of moving average filter (MAF), a novel hybrid filter in dq-frame is designed and on the basis of this design a new synchronous reference frame phase locked loop (SRF-PLL) design approach based on the hybrid filter is proposed. The proposed approach employs moving average filter (MAF) to block the high-frequency harmonics in the grid voltage, and uses DSOCCF dc to separate the fundamental frequency positive and negative sequence and reject DC offset. It can accurately extract the synchronization information of the grid fundamental frequency positive sequence. After simulation and experiment verification, it can be confirmed that the proposed PLL can quickly and accurately lock the properties of the grid voltage under adverse grid condition, and also have high detection accuracy and strong robustness to frequency fluctuations. INDEX TERMS Dual second-order complex coefficient filter (DSOCCF), harmonic, phase-locked loop (PLL), dc offset, moving average filter (MAF).

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“…Phase-locked loop (PLL) is one of the essential key grid synchronization technologies in three-phase system applications [4], [5]. It has extremely strict requirements on the dynamic performance and the phase quality.…”

Section: Introductionmentioning

confidence: 99%

A Novel Grid Synchronization Method Based on Hybrid Filter Under Distorted Voltage Conditions

et al. 2020

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The phase-locked accuracy of conventional phase-locked method is reduced when the grid voltage contains fundamental frequency negative sequence(FFNS) component, harmonic component, and DC offset component. Aiming at this problem, a novel adaptive notch filter (NANF) is proposed, and a dual NANF (DNANF) structure is designed to eliminate the FFNS component and extract the fundamental frequency positive sequence(FFPS) component based on NANF. Furthermore, dcDNANF with DC offset rejection capability is proposed by adopting DNANF. Then a novel hybrid filter in dq-frame is designed by combining dcDNANF and the cascaded delay signal cancellation operator filter whose delay parameters are 4 and 24 in dq-frame (dqCDSC 4,24). Meanwhile, a new SRF-PLL design method is proposed based on the novel hybrid filter. This proposed method employs dqCDSC 4,24 to separate the positive and negative sequences of the voltage and eliminate the high frequency harmonics in the grid voltage, and uses dcDNANF to reject the DC offset, so as to achieve the accurate acquisition of the fundamental voltage information under distortion and unbalanced grid. Simulation and experimental results show that compared with the conventional SRF-PLL methods, the proposed method can obtain faster phase tracking speed, better phase-locked effect, faster dynamic response, and better stability. INDEX TERMS Novel adaptive notch filter (NANF), harmonic, phase-locked loop (PLL), dc offset, cascaded delay signal cancellation (CDSC).

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PLL with frequency and initial‐phase‐angle detectors: performance analysis and speed/robustness trade‐off improvement

Cited by 7 publications

References 31 publications

A Non-Adaptive Single-Phase PLL Based on Discrete Half-Band Filtering to Suppress Severe Frequency Disturbances

A Non-Adaptive Single-Phase PLL Based on Discrete Half-Band Filtering to Suppress Severe Frequency Disturbances

Design of a High Performance Phase-Locked Loop With DC Offset Rejection Capability Under Adverse Grid Condition

A Novel Grid Synchronization Method Based on Hybrid Filter Under Distorted Voltage Conditions

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