Effect of Substrate Bias and Temperature Variation in the Capacitive Coupling of SOI UTBB MOSFETs

Abstract

In this work, the electrical features related to the capacitive coupling and temperature influence of the Ultra-Thin Body and Buried Oxide SOI MOSFET (UTBB) transistors are explored through numerical simulations. The impact of the substrate bias is observed for a set of values ranging from -3 V to 2 V for a temperature range between 100 K and 400 K. Also, structures with different types of ground plane (GP-P and GPN) and without GPhave been evaluated. This approach analyzes the capacitive coupling through the body factor and shows that the negative biasing for all GP types significantly improves the structure coupling and that the device with P-type ground plane has the lowest value of body factor for all the evaluated conditions. The dependence of the body factor on the temperature has shown to be negligible for longer devices. However, for devices shorter than 50 nm, the position of the maximum electrons concentration inside the silicon layer may affect the capacitive coupling.

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