on the operation of the JNTs has been also performed, showing that the zero temperature coefficient point, in which the current is the same independent of the temperature, can or not exist depending on the series resistance and its dependence on the temperature. Finally, the operation of junctionless nanowire transistors in analog applications has been analyzed for devices of different dimensions.
In this work, the electrical features related to the capacitive coupling and temperature influence of the Ultra-Thin Body and Buried Oxide SOI MOSFET (UTBB) transistors are explored through numerical simulations. The impact of the substrate bias is observed for a set of values ranging from -3 V to 2 V for a temperature range between 100 K and 400 K. Also, structures with different types of ground plane (GP-P and GPN) and without GPhave been evaluated. This approach analyzes the capacitive coupling through the body factor and shows that the negative biasing for all GP types significantly improves the structure coupling and that the device with P-type ground plane has the lowest value of body factor for all the evaluated conditions. The dependence of the body factor on the temperature has shown to be negligible for longer devices. However, for devices shorter than 50 nm, the position of the maximum electrons concentration inside the silicon layer may affect the capacitive coupling.
A MOSFET model parameters extraction procedure that overcomes the difficulties of separating the effects of source-and-drain series resistance and mobility degradation factor is presented. Instead of the conventional direct fitting, the present procedure involves the use of indirect bidimensional fitting of the source-to-drain resistance of a single device, as obtained from the below-saturation output characteristics measured at several above-threshold gate voltages. The procedure is verified with a simulated long channel FinFET device with externally added resistances and is later applied to experimental planar bulk DRAM MOSFET devices with channel lengths ranging from 0.23μm to 2.0μm. The procedure is shown to be advantageous in terms of computational efficiency and it is appropriate even with high values of externally added series resistances. For the case of devices with various channel lengths, the accuracy of the procedure is improved if the value of RSD is extracted from the shortest channel length. This value of RSD could be used for extracting the other parameters for devices with longer channel.
The main goal of this paper is to present the behavior of the substrate effect in Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs with respect to the back gate bias (VSUB) through DC and AC simulations validated to experimental data. Different ground plane (GP) arrangements have been considered in order to enhance the analysis. It has been shown that the substrate effect is strongly influenced by the reduction of the back gate bias and, that the capacitive coupling of the structure presents a different behavior with respect of each kind of GP configuration as the back gate bias is varied. Finally, it has been shown that the GP below the source and drain regions contributes significantly to the overall capacitive coupling of the transistors.
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