A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI

Lefebvre, Martin; Flandre, Denis; Bol, David

doi:10.1109/jssc.2023.3240209

Cited by 1 publication

(14 citation statements)

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“…i r is found by replacing V S by V D in (4), but is only relevant when the transistor is not saturated. It should be noted that, in what follows, the obtained expressions only slightly differ from the ones obtained in [12] due to the body connection of M 2 to ground. We have nonetheless chosen to detail them here to avoid any mistake and to provide all the necessary tools for implementing the proposed reference.…”

Section: A Self-cascode Mosfetmentioning

confidence: 57%

“…2(a) in its basic form, i.e., without calibration circuit. It also details the operation principle of the reference, and explains how the limitations of the SCM-based β-multiplier current reference in [12] have been overcome in Section II-C.…”

Section: Governing Equations and Operating Principlementioning

confidence: 99%

“…1(a) and (c)]. Previous works have shown that self-cascode MOSFETs (SCMs) are more appropriate to generate a nA-range current [10], [11], but need to be biased by a proportional-to-absolutetemperature (PTAT) voltage with a constant-with-temperature (CWT) offset to make the current CWT [12]. A temperature coefficient (TC) calibration mechanism is also necessary to maintain performance across process corners, but is difficult to integrate in the β-multiplier architecture proposed in [12].…”

Section: Introductionmentioning

confidence: 99%

“…In addition, the value of the CWT offset in [12] depends solely on technological parameters and cannot be tuned through transistor sizes. This makes the attainable performance heavily reliant on technology, potentially leading to some degradation when the CWT offset is not adapted.…”

Section: Introductionmentioning

confidence: 99%

“…In this work, we propose to fix the two critical issues of [12] mentioned hereabove by generating the SCM bias voltage with a four-transistor (4T) voltage reference. This structure includes a calibration mechanism to tune the TC in process corners, makes the CWT offset dependent on transistor sizes, and removes the need for a startup circuit.…”

Section: Introductionmentioning

confidence: 99%

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A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/$^\circ$C CMOS-Only Current Reference in 0.11-$\mu$m Bulk and 22-nm FD-SOI

Lefebvre,

Bol

2024

IEEE J. Solid-State Circuits

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Internet-of-Things (IoT) applications require nW-power current references that are robust to process, voltage and temperature (PVT) variations, to maintain the performance of IoT sensor nodes in a wide range of operating conditions. However, nA-range current references are rarely area-efficient due to the use of large gate-leakage transistors or resistors, which occupy a significant silicon area at this current level. In this paper, we introduce a nA-range constant-with-temperature (CWT) current reference, relying on a self-cascode MOSFET (SCM) biased by a four-transistor ultra-low-power voltage reference through a single-transistor buffer. The proposed reference includes a temperature coefficient (TC) calibration mechanism to maintain performance across process corners. In addition, as the proposed design relies on the body effect, it has been fabricated and measured in 0.11-µm bulk and 22-nm fully-depleted silicon-on-insulator (FD-SOI) to demonstrate feasibility in both technology types. On the one hand, the 0.11-µm design consumes a power of 16.8 nW at 1.2 V and achieves a 2.3-nA current with a line sensitivity (LS) of 2.23 %/V at 25 • C and a TC of 176 ppm/ • C at 1.2 V from -40 to 85 • C. On the other hand, the 22-nm design consumes a power of 16.3 nW at 1.5 V and achieves a 2.5-nA current with a 1.53-%/V LS at 25 • C and an 82-ppm/ • C TC at 1.5 V from -40 to 85 • C. Thanks to their simple architecture, the proposed references achieve a silicon area of 0.0106 mm 2 in 0.11 µm and 0.0026 mm 2 in 22 nm without compromising other figures of merit, and are thus competitive with state-of-the-art CWT references operating in the same current range.

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Section: A Self-cascode Mosfetmentioning

confidence: 57%

Section: Governing Equations and Operating Principlementioning

confidence: 99%