Effect of Stress on Magnetic Performance of GMR Head Used for Hard-Disk Drive

Naka, Yasuhiro; Doi, H.; Koyanagi, Hajime; Ishikawa, Chiaki

doi:10.1299/jsmea.47.62

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2010

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“…Two-step 3D multilevel modeling was used to bridge the gap of the scale difference between the package and the film stack. 18) At the first level, a quarter of the QFP was modeled using symmetric boundary conditions. The first level included the chip, a frame, and a resin.…”

Section: Stress Simulation Modelmentioning

confidence: 99%

Stress Analysis for Chip–Package Interaction of Cu/Low-k Multilayer Interconnects

Kumagai¹,

Ohta²,

Fujisawa

et al. 2010

Jpn. J. Appl. Phys.

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Delamination failure of a low-k interlayer dielectric (ILD) layer of Cu/low-k multilayer interconnects during a thermal cycle test was investigated by mechanical stress simulation. A three-dimensional (3D) multilevel modeling method was used to analyze the stress that occurred in a fine-scale film stack in a large-scale package. The maximum stress occurred at the low-k/cap film interface that was located at the bottom surface of the low-k ILD layer. This maximum-stress interface coincides with the interface where the delamination occurred. Using this method, the effects of the number of ILD layers, the Young's modulus of the ILD, and the package type on the failure were investigated. This method is useful for reducing delamination failure.

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Section: Stress Simulation Modelmentioning

confidence: 99%