Effect of SiC Power DMOSFET Threshold-Voltage Instability

Lelis, Aivars J.; Habersat, Daniel B.; Green, R.; Ogunniyi, Aderinto; Gurfinkel, M.; Suehle, John S.; Goldsman, N.

doi:10.1557/proc-1069-d11-04

Cited by 5 publications

(4 citation statements)

References 12 publications

(20 reference statements)

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“…The shift in V DS required to supply 20 A when V GS = +15 V is a little more than 0.1 V, which is an increase of about 7 percent. This increase in on-state resistance is comparable to what was calculated based on fast I-V measurements of bias-stress instability results [5].…”

Section: Resultssupporting

confidence: 87%

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Implications of Threshold-Voltage Instability on SiC DMOSFET Operation

Lelis

Habersat

Green

et al. 2009

MSF

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Although recent fast I-V measurements and subthreshold analysis reveal that the threshold-voltage instability due to low-field bias stressing at room temperature is greater than previously reported when calculated using slower, standard measurements by a parameter analyzer—a result that is consistent with electrons directly tunneling into and out of near interfacial oxide traps, this effect will not prevent the use of power SiC DMOSFET switches in power converter applications if certain precautions are followed. Namely, if the threshold voltage is set high enough so that a negative shift in threshold voltage will not increase the leakage current in the off-state, then the primary effect will be to increase the on-state resistance by decreasing the effective gate voltage. The instability due to ON-state stressing is greater than that for bias stressing alone, but not significantly. For a well behaved device, a 1-hour ON-state stress will result in about a 7 percent increase in conduction losses, which is manageable for power converter applications.

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Section: Resultssupporting

confidence: 87%

“…Furthermore, this effect is repeatable and has been observed in all 4H and 6H SiC MOSFETs from several different manufacturers [4]. It has also been observed in both lateral test structures and vertical power devices [5,6].…”

Section: Introductionsupporting

confidence: 68%

Implications of Threshold-Voltage Instability on SiC DMOSFET Operation

Lelis

Habersat

Green

et al. 2009

MSF

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“…[26][27][28] Due to the dramatic decrease in effective carrier concentration in SiC over the measured temperature range, the sample exhibited V th increase from about 0.73 V at room temperature to 7.4 V at 40 K, as extracted from the x-intercept of the I D versus V GS curve at V DS = 0.1 V. This change in V th indicated a net negative charge of 3 9 10 12 cm À2 present in the oxide. The field-effect mobility (l FE ) decreased from 26.9 cm 2 /V s at room temperature to less than 5 cm 2 /V s below 100 K, as previously reported in the literature.…”

Section: Tsc Spectra Of Mos Transistorsmentioning

confidence: 95%

Spatial Localization of Carrier Traps in 4H-SiC MOSFET Devices Using Thermally Stimulated Current

Tadjer

Stahlbush

Hobart

et al. 2010

Journal of Elec Materi

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Carrier traps in 4H-SiC metal-oxide-semiconductor (MOS) capacitor and transistor devices were studied using the thermally stimulated current (TSC) method. TSC spectra from p-type MOS capacitors and n-channel MOS fieldeffect transistors (MOSFETs) indicated the presence of oxide traps with peak emission around 55 K. An additional peak near 80 K was observed due to acceptor activation and hole traps near the interface. The physical location of the traps in the devices was deduced using a localized electric field approach. The density of hole traps contributing to the 80-K peak was separated from the acceptor trap density using a gamma-ray irradiation method. As a result, hole trap density of N t,hole = 2.08 9 10 15 cm À3 at 2 MV/cm gate field and N t,hole = 2.5 9 10 16 cm À3 at 4.5 MV/cm gate field was extracted from the 80-K TSC spectra. Measurements of the source-body n + -p junction suggested the presence of implantation damage in the space-charge region, as well as defect states near the n + SiC substrate.

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“…The gate voltage sweeping rate (mV/s) or sweeping time influences the magnitude of V th shift [32][33][34]. Figure 2 shows V th hysteresis as a function of measurement sweep time [32].…”

Section: Sweeping Ratementioning

confidence: 99%

Bias temperature instability in SiC metal oxide semiconductor devices

Yang¹,

Wei²,

Wang³

2021

J. Phys. D: Appl. Phys.

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Although silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) are commercially available, bias temperature instability (BTI) defined as shifts in V th in SiC MOSFET and V fb in MOS capacitor after the device is operated at a high temperature, seriously affects device reliability and limits further commercial applications. These instabilities are mainly attributed to charge trapping at and near the SiC/SiO 2 interface and mobile ions in a gate oxide. The consequences of V th instability are serious and can worsen the performance and lifetime of SiC MOS devices. In this review, the SiC/SiO 2 interface issue is introduced, and BTI occurring in current SiC MOS devices is described in detail. V th /V fb instability behavior induced by measurement and stress conditions, microscopic defects and instability mechanisms, recent measurement techniques of near-interfacial oxide traps, and BTI improvement resulting from the fabrication processes are described. BTI improvement mainly involves the control of charge trapping and movements of ions. The fabrication processes are related to oxidation and pre-and post-oxidation treatments. This review can help deepen our understanding of BTI and reduce its influence on SiC MOS devices performance.

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Effect of SiC Power DMOSFET Threshold-Voltage Instability

Cited by 5 publications

References 12 publications

Implications of Threshold-Voltage Instability on SiC DMOSFET Operation

Implications of Threshold-Voltage Instability on SiC DMOSFET Operation

Spatial Localization of Carrier Traps in 4H-SiC MOSFET Devices Using Thermally Stimulated Current

Bias temperature instability in SiC metal oxide semiconductor devices

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