Spatial Localization of Carrier Traps in 4H-SiC MOSFET Devices Using Thermally Stimulated Current

Abstract

Carrier traps in 4H-SiC metal-oxide-semiconductor (MOS) capacitor and transistor devices were studied using the thermally stimulated current (TSC) method. TSC spectra from p-type MOS capacitors and n-channel MOS fieldeffect transistors (MOSFETs) indicated the presence of oxide traps with peak emission around 55 K. An additional peak near 80 K was observed due to acceptor activation and hole traps near the interface. The physical location of the traps in the devices was deduced using a localized electric field approach. The density of hole traps contributing to the 80-K peak was separated from the acceptor trap density using a gamma-ray irradiation method. As a result, hole trap density of N t,hole = 2.08 9 10 15 cm À3 at 2 MV/cm gate field and N t,hole = 2.5 9 10 16 cm À3 at 4.5 MV/cm gate field was extracted from the 80-K TSC spectra. Measurements of the source-body n + -p junction suggested the presence of implantation damage in the space-charge region, as well as defect states near the n + SiC substrate.

Radiation Hardness of Silicon Carbide upon High-Temperature Electron and Proton Irradiation

“…Our work is focused on the results of high-temperature irradiation, due to the fact that a lot of works have been devoted to the study and analysis of the results of irradiation at room temperature. The great number of published studies are concerned with the radiation hardness of SiC MOSFETs against γirradiation [ 6 , 7 , 8 , 9 , 10 , 11 , 12 ]. The effect of room temperature electron irradiation on the properties of high-voltage 4H-SiC Schottky diodes also has been studied in many works [ 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 ].…”

Identification of a major cause of endemically poor mobilities in SiC/SiO2 structures

“…Thus, either N i attacks any HK0 that may have formed or simply captures the diffusive C i interstitials and pre-empts HK0 formation. Tadjer et al have reported a hole trap located in the SiC epilayer in 4H-SiC MOS capacitors and transistors 33 . The energy level of the hole trap is found to overlap with the Al acceptor level in SiC, which is around E v +0.22 eV 34 .…”

Gate Oxide Stability of 4H-SiC MOSFETs under On/Off-State Bias-Temperature Stress

“…When drain bias was applied during stress (ON-state positive stress), channel depletion near the drain allowed gate field penetration away from the SiO2/SiC interface into the SiC bulk. The presence of hole traps in the bulk SiC has been experimentally observed [3] and attributed to immobile carbon di-interstitial defects in the SiC [4]. Our hypothesis is that at room temperature hole traps in the bulk were filled during positive gate field stress, which lead to two consequences.…”