1986
DOI: 10.1063/1.97465
|View full text |Cite
|
Sign up to set email alerts
|

Effect of post-oxidation anneal on ultrathin SiO2 gate oxides

Abstract: Ultrathin silicon oxide films 5–6 nm thick have been grown in a double-walled furnace and annealed in N2 and Ar at temperatures varying between 850 and 1100 °C. The breakdown field distribution obtained is very tight and centered above 11 MV/cm for as-grown oxides at 850 °C. The oxides that received a post-oxidation anneal (POA) at 1000 °C show a consistent improvement in breakdown field distribution and breakdown charge density as compared to the oxides annealed at lower temperatures. Furthermore, under high … Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

1
9
0

Year Published

1988
1988
2018
2018

Publication Types

Select...
7
1
1

Relationship

0
9

Authors

Journals

citations
Cited by 20 publications
(10 citation statements)
references
References 17 publications
1
9
0
Order By: Relevance
“…We fabricate the devices in the following procedure: first, 10 nm SiO 2 is grown on RCAcleaned n-Si (001) substrates (average resistivity = 0.04 ohm• cm) by dry oxidation at 1000 °C for 15 min, followed by N 2 annealing at 1000 °C for 1 h to improve the interface quality. 48 Then Sn nanostructures with a nominal thickness of 20 nm are evaporated at 0.2 Å/s onto the SiO 2 layer. For solar-blind UV detectors, the Sn nanostructures are deposited through various sizes of mask openings ranging from 50 × 50 μm 2 to 2 × 2 mm 2 .…”
Section: Acs Photonicsmentioning
confidence: 99%
“…We fabricate the devices in the following procedure: first, 10 nm SiO 2 is grown on RCAcleaned n-Si (001) substrates (average resistivity = 0.04 ohm• cm) by dry oxidation at 1000 °C for 15 min, followed by N 2 annealing at 1000 °C for 1 h to improve the interface quality. 48 Then Sn nanostructures with a nominal thickness of 20 nm are evaporated at 0.2 Å/s onto the SiO 2 layer. For solar-blind UV detectors, the Sn nanostructures are deposited through various sizes of mask openings ranging from 50 × 50 μm 2 to 2 × 2 mm 2 .…”
Section: Acs Photonicsmentioning
confidence: 99%
“…Much work has been done to improve the quality and reduce defect density of the as-grown oxide (15)(16)(17). The effects of other processing in CMOS technologies on the quality of the oxide has also been a subject of intensive study; for example, intrinsic and extrinsic gettering in the front-end processing (18)(19)(20)(21)(22), high-temperature treatments after gate polysilicon deposition (15,(23)(24)(25), reactive ion etching (26)(27)(28)(29), ion implantation and annealing (14,30), postmetal annealing (31), and final passivation film deposition (32). However, most of the studies concerning the breakdown phenomenon in silicon dioxide have employed simple, minimally processed MOS capacitors.…”
mentioning
confidence: 99%
“…17 For devices in the submicron range for metal-oxidesemiconductor very large scale integration ͑MOS VLSI͒, it is necessary to fabricate SiO 2 films with thicknesses around 100 Å in a repeatable manner. Several methods have been put forward for the fabrication of very thin high-quality silicon dioxides based on thermal oxidation processes, [20][21][22][23] but the thermal oxidation processes always involve high processing temperatures ͑usually Ͼ800°C͒, which would give rise to several undesirable diffusion-related and high temperature-sensitive effects that may hinder the performance of small MOS devices and other integrated circuit components. A low temperature processing for fabrication of silicon dioxides can be performed using plasma enhanced chemical vapor deposition ͑PECVD͒ processes.…”
Section: Introductionmentioning
confidence: 99%