Breakdown Yield and Lifetime of Thin Gate Oxides in CMOS Processing

Abstract

The processing effects on thin gate oxide yield and lifetime were studied by using ramp voltage and time-dependent dielectric breakdown (TDDB) measurements on minimally processed MOS capacitors and fully processed devices in a CMOS technology. Gate oxides grown in a wet ambient are considerably superior to those grown in a dry 02 ambient interms of breakdown distribution, yield, and lifetime. In addition, the correlation between lifetime and applied electric field also suggests an advantage for using wet oxides rather than dry oxides for scaling down the thickness. Several processing modules in a CMOS technology on the gate oxide breakdown characteristics are examined. High temperature oxidatiqn and drive or back-side gettering processing prior to the gate oxidation steps improve the oxide yield. Reactive ion or plasma etching for the gate electrode definition reduces lifetime of approximately 10% of the devices compared to the wet-etched control. However, the most significant influence on the gate oxide yield and lifetime occurs during the oxidation and polysilicon gate deposition processing steps. Fully processed CMOS devices show a large reduction in gate oxide yield and lifetime as compared to minimally processed capacitors. Additional processing for double level meta]lization further degrades the gate oxide. This result indicates the cumulative nature of processing induced damage. Breakdown characteristics are significantly degraded when electrons are injected from the polysilicon gate as opposed to injection from the silicon substrate for the fully processed devices. This polarity dependence can be explained by plasma processing induced trapped holes near the polysilicon/SiO2 interface which also cause anomalous leakage currents with a negative gate bias.

Adding functionality to microchips by wafer post-processing

“…Of course, newly added layers should adhere well and survive subsequent processing. Additional, important guidelines at the end of the metallization stage are: the wafer temperature should not exceed 425-450 1C, or the pre-existing metallization will degrade through various mechanisms [5]; when a plasma process is employed, the risk of charging of the MOS transistors should be assessed [6,7];…”

<title>GaAs heteroepitaxy with submicron Si CMOS: an experimental compatibility study</title>

“…GaAs heteroepitaxy and GaAs device fabrication may impact the interface/oxide charge [17] and oxide wearout [18] of deep submicron CMOS devices.…”

Plasma induced wafer charging sensor

“…It becomes a serious problem especially in sub-micron features [15]. With the continued decrease in gate oxide thickness to improve MOS device performance, damage due to gate charging has been appearing after various plasma processing steps, with etching and ashing being of most concern [7,9,16]. The damage can degrade all the electrical properties of a gate oxide [6] which include the fixed oxide charge density, the interface state density, the flat band voltage, the leakage current and the various breakdown related parameters.…”