Effect of low-k dielectric on stress and stress-induced damage in Cu interconnects

Paik, Jong-Min; Park, Hyun; Joo, Young‐Chang

doi:10.1016/j.mee.2004.02.094

Cited by 71 publications

(41 citation statements)

References 31 publications

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“…• C, 216,217 and this has been one of the reasons cited for their general lack of main-stream adoption for low-k/Cu interconnect fabrication. 218,219 Another thermal property of significant importance for low-k DB and ILD materials is thermal conductivity.…”

Section: -122mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

131

115

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Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore's law (i.e. More Moore) and More than Moore scaling.

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Section: -122mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

131

115

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“…Primarily, prior works (Oh et al 2013;Heryanto et al 2011;Weide-zaage 2012;Wu et al 2010;O Brien 2013;Hommel et al 2002;Paik et al 2004) have considered crystalline copper and isotropic material properties for reliability simulations. A clear dependance between the copper microstructure in nanoscale interconnects, void formation kinetics, and electromigration statistics has been established through experiments (Cao et al 2013).…”

Section: Introductionmentioning

confidence: 99%

Modeling the copper microstructure and elastic anisotropy and studying its impact on reliability in nanoscale interconnects

Basavalingappa

Shen

Lloyd

2017

Mech Adv Mater Mod Process

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Background: Copper is the primary metal used in integrated circuit manufacturing of today. Even though copper is face centered cubic it has significant mechanical anisotropy depending on the crystallographic orientations. Copper metal lines in integrated circuits are polycrystalline and typically have lognormal grain size distribution. The polycrystalline microstructure is known to impact the reliability and must be considered in modeling for better understanding of the failure mechanisms. Methods: In this work, we used Voronoi tessellation to model the polycrystalline microstructure with lognormal grainsize distribution for the copper metal lines in test structures. Each of the grains is then assigned an orientation with distinct probabilistic texture and corresponding anisotropic elastic constants based on the assigned orientation. The test structure is then subjected to a thermal stress.

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“…All interfaces are assumed to have perfect adhesion. In order to consider the thermal expansion of Si substrate, the substrate is chosen as the reference frame, and the CTE of all the other materials are adjusted relative to the substrate [7] . Figure 2 shows the contour plot of hydrostatic stress component σ h developed in the dual-damascene structure upon cooling for the model of FOx with barrier material of TaN.…”

Section: Finite Element Model Descriptionmentioning

confidence: 99%

“…Each material is assumed to be an isotropic linear elastic solid. This assumption is reasonable, because it is known that the copper line, whose width is in the sub-micrometer level, continues to show linear elastic behavior even at temperature as high as 400 ℃ [6][7][8] . The properties of the materials used in this calculation are summarized in Table 1.…”

Section: Introductionmentioning

confidence: 99%

Finite element modeling of hydrostatic stress distribution in copper dual-damascene interconnects

Chen

2011

J. Shanghai Jiaotong Univ. (Sci.)

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Hydrostatic stresses of copper dual-damascene interconnects are calculated by a commercial finite element software in this paper. The analytical work is performed to examine the effects of different low-k (k is permittivity) dielectrics, barrier layer and aspect ratio of via on hydrostatic stress distribution in the copper interconnects. The results of calculation indicate that the hydrostatic stresses are highly non-uniform throughout the copper interconnects and the highest tensile hydrostatic stress exists on the top interface of lower level interconnect near via. Both the high coefficient of thermal expansion and the low elastic modulus of the low-k dielectrics and barrier layer can decrease the highest hydrostatic stress on the top interface, which can improve the reliability of the copper interconnects.

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Effect of low-k dielectric on stress and stress-induced damage in Cu interconnects

Cited by 71 publications

References 31 publications

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Modeling the copper microstructure and elastic anisotropy and studying its impact on reliability in nanoscale interconnects

Finite element modeling of hydrostatic stress distribution in copper dual-damascene interconnects

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