Effect of loop delay on phase margin of first-order and second-order control loops

Bergmans, J.W.M.

doi:10.1109/tcsii.2005.852003

Cited by 32 publications

(15 citation statements)

References 7 publications

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“…In the simulations, the PSD of the frequency noise N p is set to 7 × 10 −11 Hz −1 (−101 dBc/Hz) [24], the damping ratio ξ is set to 1 [25], the initial phase error fraction ρ is set to 1 % [19], T ctrl is set to 200 µs, and R b is set to 2 bps/Hz. Fig.…”

Section: Simulation Resultsmentioning

confidence: 99%

Phase-level synchronization for physical-layer network coding

Huang

Song

Wang

et al. 2012

2012 IEEE Global Communications Conference (GLOBECOM)

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Abstract-Physical-layer network coding (PNC) brings throughput improvement for wireless networks. However, its synchronization requirement is widely recognized as an obstacle to its implementation. In this paper, we focus on phase-level synchronization and propose a time-slotted carrier synchronization scheme for PNC. We then analyze the phase error tolerance of PNC under different bit error rate (BER) requirements, and the synchronization overhead for obtaining synchronous signals below the phase error margin. We also consider the impact of different hardware (in particular, the phase-locked loop) parameters on the overhead in our analysis. Afterwards, we evaluate the performance of the proposed synchronization scheme with simulations. The results show that the proposed scheme is feasible with some typical hardware parameters. The throughput gain of PNC when using the proposed scheme is only slightly lower than the theoretical gain.

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Section: Simulation Resultsmentioning

confidence: 99%

Phase-level synchronization for physical-layer network coding

Huang

Song

Wang

et al. 2012

2012 IEEE Global Communications Conference (GLOBECOM)

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“…As in traditional control-loop theory, gain and phase margins needs to be achieved, and loop delays need to be understood [25][26][27].…”

Section: B Closed Loopmentioning

confidence: 99%

“…Reducing the loop bandwidth will reduce the effect until it behaves almost as a continuous loop without any delay [27].…”

Section: B Closed Loopmentioning

confidence: 99%

Analysis of communication network challenges for synchrophasor-based wide-area applications

Danielson¹,

Vanfretti

Almas

et al. 2013

2013 IREP Symposium Bulk Power System Dynamics and Control - IX Optimization, Security and Control of the Emerging Power Grid

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Abstract-Wide-area synchrophasor applications inherently depend on the underlying IT and communications infrastructure supporting them. In particular, closed loop control systems for power grid oscillation damping is problematic, as it is a complex mixture of power grid monitoring, communication network properties and overall system stability issues. This article offers a holistic analysis of these fields, proposing a combined requirement on the full system: to keep system delays down to maintain stability. Simulation results to support the analysis findings, also showing how observability of power oscillations is important in combination with system delays related to feedback signals, and finally laying out experimentation plans to be performed in the lab on a complex power-grid model with real PMUs, communication network and controllers interacting with the SmarTS Lab real-time hardware-in-the-loop simulator platform.

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“…The effects of such delays on the stability and phase margin for DT-PLLs with delays have been previously investigated [1], [2], and [3]. The effect of delays on stability, root-locus, and frequency-response, and investigation of some specific scenarios with a low number of delays is covered in [4].…”

Section: Introductionmentioning

confidence: 99%

“…Transient behavior is often described by the second-order notions of damping factor ζ and natural frequency ω n . [1], [2], and other references on DT-PLLs …”

Section: Introductionmentioning

confidence: 99%

Parameter Derivation of Type-2 Discrete-Time Phase-Locked Loops Containing Feedback Delays

Wilson

Nelson

Farhang‐Boroujeny

2009

IEEE Trans. Circuits Syst. II

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Abstract-Modern implementations of discrete-time phaselocked loops (DT-PLLs) often contain delayed feedback. The delays are usually a side effect to pipelining, filtering, or other inner-loop mechanisms. Each delay increases the order of the system by introducing an additional pole to the closed-loop transfer function, and in many cases, makes the traditional type-2 loop equations obsolete. This paper describes how the secondorder notions of damping and natural frequency can be applied to type-2 DT-PLLs in the presence of any number of delays. It provides equations for loop parameters that will provide a desired transient behavior based on damping and natural frequency, along with a test to ensure the accuracy of the results. The novelty of this work is that loop parameters can be found in closedform and ensured to be accurate, without the need for human interaction, simulations, or numerical root-finding algorithms.

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Effect of loop delay on phase margin of first-order and second-order control loops

Cited by 32 publications

References 7 publications

Phase-level synchronization for physical-layer network coding

Phase-level synchronization for physical-layer network coding

Analysis of communication network challenges for synchrophasor-based wide-area applications

Parameter Derivation of Type-2 Discrete-Time Phase-Locked Loops Containing Feedback Delays

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