2009
DOI: 10.1109/tcsii.2009.2034197
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Parameter Derivation of Type-2 Discrete-Time Phase-Locked Loops Containing Feedback Delays

Abstract: Abstract-Modern implementations of discrete-time phaselocked loops (DT-PLLs) often contain delayed feedback. The delays are usually a side effect to pipelining, filtering, or other inner-loop mechanisms. Each delay increases the order of the system by introducing an additional pole to the closed-loop transfer function, and in many cases, makes the traditional type-2 loop equations obsolete. This paper describes how the secondorder notions of damping and natural frequency can be applied to type-2 DT-PLLs in the… Show more

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Cited by 9 publications
(6 citation statements)
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“…Subsequently, while the carrier and timing tracking loops were active or deactivated, the performance of the receiver in detecting the payload information symbols was studied. For the carrier tracking loop filter we followed [62] and designed a proportional and integrator loop that also counts for the delay caused by the analysis filter bank. The filter parameters that were calculated for a critically damped PLL were obtained as K p = 0.1208, for the proportional gain, and K I = 0.0068, for the integrator gain.…”
Section: Simulation Resultsmentioning
confidence: 99%
“…Subsequently, while the carrier and timing tracking loops were active or deactivated, the performance of the receiver in detecting the payload information symbols was studied. For the carrier tracking loop filter we followed [62] and designed a proportional and integrator loop that also counts for the delay caused by the analysis filter bank. The filter parameters that were calculated for a critically damped PLL were obtained as K p = 0.1208, for the proportional gain, and K I = 0.0068, for the integrator gain.…”
Section: Simulation Resultsmentioning
confidence: 99%
“…This modification inserts additional delay in the loop which is not accounted for in the standard PLL transfer function. Following the lead of Wilson, Nelson, and Farhang-Boroujeny [3], we presented the appropriately modified transfer function and then demonstrated how the additional roots inserted by the matched filter delays influence the dominant roots of the design process.…”
Section: Discussionmentioning
confidence: 99%
“…We suggest the reader also examine [3] which presents a design procedure that incorporates the effect of the excess delays in the design process.…”
Section: Discussionmentioning
confidence: 99%
See 1 more Smart Citation
“…We initially considered the delay of the FIR filter when tweaking the coefficients, as in [37], but the demodulator was still plagued by frequent losses of lock and low output SNR. The best results were obtained with the values reported in atpdec's [38] code.…”
Section: Rtl-sdr Library For Simulinkmentioning
confidence: 99%